GLAST / LAT > DAQ and FSW > FSW > Doxygen Index> LEM / V4-8-1 > lem_bci / linux-gcc
Enumerations | |
| enum | LEM_FUNCTION { CMD_DATALESS = 0, CMD_LOAD = 1, CMD_READ = 2, ACD_CMD_DATALESS = 1, ACD_CMD_LOAD = 1, ACD_CMD_READ = 3 } |
| Sybmols for the function of a LATp packet. | |
| enum | LEM_OPCODE { LEM_OPCODE_NOOP = 0, LEM_OPCODE_RESET = 1, GEM_OPCODE_SOLICIT_TRIGGER = 2, EBM_OPCODE_STAT_RESET = 0, CRC_OPCODE_CALSTROBE = 3, ARC_OPCODE_SET_HVBS = 10, ARC_OPCODE_SET_HVSAA = 11 } |
| Enumeration of the LATp opcodes. | |
| enum | LEM_REG_ID { CRU_CONFIGURATION = 0, CRU_COMMAND = 1, CRU_RESPONSE = 2, CRU_CR_STATS = 3, CRU_ACD_STARTUP_CLOCK = 4, CRU_TEST_IO = 5, GEM_CON_CONFIGURATION = 0, GEM_CON_ADDRESS = 1, GEM_CON_WINDOW = 2, GEM_CON_PERIODIC_MODE = 3, GEM_CON_PERIODIC_LIMIT = 4, GEM_CON_PERIODIC_RATE = 5, GEM_CON_SEQUENCE = 6, GEM_CON_CR_STATS = 7, GEM_CON_EVT_STATS = 8, GEM_CON_DELAY_EXT_TRG = 9, GEM_WIN_WIDTH = 0, GEM_WIN_OPEN_MASK = 1, GEM_STAT_LIVETIME = 0x0, GEM_STAT_PRESCALE = 0x1, GEM_STAT_DISCARD = 0x2, GEM_STAT_SENT = 0x3, GEM_STAT_TILE_COUNTERS = 0x4, GEM_STAT_TILE_0 = 0x5, GEM_STAT_TILE_1 = 0x6, GEM_STAT_CNO_COUNTERS = 0x7, GEM_STAT_CNO_0 = 0x8, GEM_STAT_CNO_1 = 0x9, GEM_STAT_1_PPS = 0xa, GEM_STAT_TIMEBASE = 0xb, GEM_STAT_DEAD_ZONED = 0xc, GEM_TAM_ENGINE_0 = 0x0, GEM_TAM_ENGINE_1 = 0x1, GEM_TAM_ENGINE_2 = 0x2, GEM_TAM_ENGINE_3 = 0x3, GEM_TAM_ENGINE_4 = 0x4, GEM_TAM_ENGINE_5 = 0x5, GEM_TAM_ENGINE_6 = 0x6, GEM_TAM_ENGINE_7 = 0x7, GEM_TAM_ENGINE_8 = 0x8, GEM_TAM_ENGINE_9 = 0x9, GEM_TAM_ENGINE_A = 0xa, GEM_TAM_ENGINE_B = 0xb, GEM_TAM_ENGINE_C = 0xc, GEM_TAM_ENGINE_D = 0xd, GEM_TAM_ENGINE_E = 0xe, GEM_TAM_ENGINE_F = 0xf, GEM_SCHD_CON_00_07 = 0x00, GEM_SCHD_CON_08_0F = 0x01, GEM_SCHD_CON_10_17 = 0x02, GEM_SCHD_CON_18_1F = 0x03, GEM_SCHD_CON_20_27 = 0x04, GEM_SCHD_CON_28_2F = 0x05, GEM_SCHD_CON_30_37 = 0x06, GEM_SCHD_CON_38_3F = 0x07, GEM_SCHD_CON_40_47 = 0x08, GEM_SCHD_CON_48_4F = 0x09, GEM_SCHD_CON_50_57 = 0x0a, GEM_SCHD_CON_58_5F = 0x0b, GEM_SCHD_CON_60_67 = 0x0c, GEM_SCHD_CON_68_6F = 0x0d, GEM_SCHD_CON_70_77 = 0x0e, GEM_SCHD_CON_78_7F = 0x0f, GEM_SCHD_CON_80_87 = 0x10, GEM_SCHD_CON_88_8F = 0x11, GEM_SCHD_CON_90_97 = 0x12, GEM_SCHD_CON_98_9F = 0x13, GEM_SCHD_CON_A0_A7 = 0x14, GEM_SCHD_CON_A8_AF = 0x15, GEM_SCHD_CON_B0_B7 = 0x16, GEM_SCHD_CON_B8_BF = 0x17, GEM_SCHD_CON_C0_C7 = 0x18, GEM_SCHD_CON_C8_CF = 0x19, GEM_SCHD_CON_D0_D7 = 0x1a, GEM_SCHD_CON_D8_DF = 0x1b, GEM_SCHD_CON_E0_E7 = 0x1c, GEM_SCHD_CON_E8_EF = 0x1d, GEM_SCHD_CON_F0_F7 = 0x1e, GEM_SCHD_CON_F8_FF = 0x1f, GEM_IE_TOWERS_00_03 = 0x00, GEM_IE_TOWERS_04_07 = 0x01, GEM_IE_TOWERS_08_11 = 0x02, GEM_IE_TOWERS_12_15 = 0x03, GEM_IE_ACD_CNO = 0x04, GEM_IE_TILES_000_013 = 0x05, GEM_IE_TILES_014_032 = 0x06, GEM_IE_TILES_033_NA3 = 0x07, GEM_IE_TILES_100_113 = 0x08, GEM_IE_TILES_114_NA5 = 0x09, GEM_IE_TILES_200_213 = 0x0a, GEM_IE_TILES_214_NA7 = 0x0b, GEM_IE_TILES_300_313 = 0x0c, GEM_IE_TILES_314_NA9 = 0x0d, GEM_IE_TILES_400_413 = 0x0e, GEM_IE_TILES_414_NA1 = 0x0f, GEM_IE_TILES_500_NA10 = 0x10, GEM_IE_TOWER_BUSY = 0x11, GEM_IE_EXTERNAL = 0x12, PDU_CONFIGURATION = 0, PDU_ADDRESS = 1, PDU_CR_STATS = 2, PDU_CRATES = 3, PDU_TEMS = 4, PDU_ACD = 5, PDU_MONITOR = 6, EBM_BACK_END_CFG = 0x0, EBM_FRONT_END_CFG_A = 0x1, EBM_FRONT_END_CFG_B = 0x2, EBM_ADDRESS = 0x3, EBM_INPUT_ENABLES = 0x4, EBM_CONTRIBUTORS = 0x5, EBM_DESTINATION_ENABLES = 0x6, EBM_TIMEOUT = 0x7, EBM_TEM_STATS = 0x8, EBM_CR_STATS = 0x9, EBM_SSR_HDR = 0xa, EBM_RECEIVE_GEM = 0, EBM_RECEIVE_AEM = 1, EBM_RECEIVE_SIU0 = 2, EBM_RECEIVE_SIU1 = 3, EBM_RECEIVE_EPU0 = 4, EBM_RECEIVE_EPU1 = 5, EBM_RECEIVE_EPU2 = 6, EBM_RECEIVE_SIU2 = 7, EBM_RECEIVE_TEM_MUX0 = 16, EBM_RECEIVE_TEM_MUX1 = 17, EBM_TRANSMIT_SIU0 = 32, EBM_TRANSMIT_SIU1 = 33, EBM_TRANSMIT_EPU0 = 34, EBM_TRANSMIT_EPU1 = 35, EBM_TRANSMIT_EPU2 = 36, EBM_TRANSMIT_SIU2 = 37, EBM_TRANSMIT_SSR = 38, TEM_CONFIGURATION = 0, TEM_DATA_MASKS = 1, TEM_STATUS = 2, TEM_CMD_RSP_STATS = 3, TEM_TKR_TRGSEQ = 4, TEM_CAL_TRGSEQ = 5, TEM_ADDRESS = 6, CCC_CONFIGURATION = 0, CCC_LAYER_MASK_0 = 1, CCC_LAYER_MASK_1 = 2, CCC_FIFO_STATUS = 3, CCC_LATCHED_STATUS = 4, CCC_EVENT_TIMEOUTS = 5, CCC_TRG_ALIGNMENT = 6, CRC_STATUS = 0, CRC_LAST_CMD = 1, CRC_DELAY_1 = 3, CRC_DELAY_2 = 4, CRC_DELAY_3 = 5, CRC_DAC = 6, CRC_CONFIG = 7, CFE_CONFIG_0 = 0, CFE_CONFIG_1 = 1, CFE_FLE_DAC = 2, CFE_FHE_DAC = 3, CFE_LOG_ACPT = 4, CFE_RNG_ULD_DAC = 5, CFE_REF_DAC = 6, TCC_CONFIGURATION = 0, TCC_INPUT_MASK = 1, TCC_FIFO_STATUS = 2, TCC_LATCHED_STATUS = 3, TCC_EVENT_TIMEOUTS = 4, TCC_TRG_ALIGNMENT = 5, TRC_CSR = 0, TRC_SYNCH = 1, TFE_DATA_MASK = 0, TFE_CALIB_MASK = 1, TFE_TRIG_MASK = 2, TFE_DAC = 3, TFE_MODE = 4, TIC_POWER_SUPPLY = 0, TIC_STATUS = 1, TIC_CAL_INPUT_MASK = 2, TIC_CAL_LRS_MASK = 3, TIC_CAL_LRS_COUNTERS = 4, TIC_TKR_INPUT_MASK_0 = 5, TIC_TKR_INPUT_MASK_1 = 6, TIC_TKR_INPUT_MASK_2 = 7, TIC_TKR_LAYER_ENABLE_0 = 5, TIC_TKR_LAYER_ENABLE_1 = 6, TIC_TKR_OUT_MASK = 7, TIC_TKR_LRS_MASK = 8, TIC_TKR_UNUSED = 9, TIC_TKR_LRS_COUNTER_A = 10, TIC_TKR_LRS_COUNTER_B = 11, TIC_TKR_LRS_COUNTER_0 = 10, TIC_TKR_LRS_COUNTER_1 = 11, TIC_BUSY_LRS_MASK = 12, TIC_BUSY_LRS_COUNTER = 13, TIC_ADCS = 14, TIC_MUX_CONFIG = 15, TIC_TKR_BIAS_DAC = 16, TIC_CAL_BIAS_DAC = 17, AEM_CON_CONFIGURATION = 0, AEM_CON_COMMON_STATUS = 1, AEM_CON_FREEBOARD_STATUS = 2, AEM_CON_COMMAND_RESPONSE = 3, AEM_CON_TRGSEQ = 4, AEM_CON_POWER_STATUS = 5, AEM_CON_ADDRESS = 6, AEM_CON_TIMEOUT = 7, AEM_CON_RELOCATION = 8, AEM_CON_RESPONSE_TIMEOUT = 9, AEM_CON_POWER_UP = 10, AEM_CON_POWER_DOWN = 11, AEM_CON_TRIGGER_STATISTICS = 12, AEM_ENV_FREE_00 = 0, AEM_ENV_FREE_01 = 1, AEM_ENV_FREE_02 = 2, AEM_ENV_FREE_03 = 3, AEM_ENV_FREE_04 = 4, AEM_ENV_FREE_05 = 5, AEM_ENV_FREE_06 = 6, AEM_ENV_FREE_07 = 7, AEM_ENV_FREE_08 = 8, AEM_ENV_FREE_09 = 9, AEM_ENV_FREE_10 = 10, AEM_ENV_FREE_11 = 11, ARC_VETO_DELAY = 2, ARC_RQST_HVBS = 8, ARC_RQST_HVSAA = 9, ARC_HVBS = 10, ARC_HVSAA = 11, ARC_HOLD_DELAY = 12, ARC_VETO_WIDTH = 13, ARC_HITMAP_WIDTH = 14, ARC_HITMAP_DEADTIME = 15, ARC_LOOK_AT_ME = 20, ARC_HITMAP_DELAY = 24, ARC_PHA_EN_0 = 25, ARC_VETO_EN_0 = 26, ARC_HLD_EN_0 = 27, ARC_PHA_EN_1 = 28, ARC_VETO_EN_1 = 29, ARC_HLD_EN_1 = 30, ARC_MAX_PHA = 31, ARC_MODE = 40, ARC_STATUS = 41, ARC_LAST_CMND = 42, ARC_LAST_CMD = 42, ARC_DIAGNOSTIC = 43, ARC_CMD_REJECT = 44, ARC_FREE_ID = 45, ARC_GARC_VERSION = 46, ARC_PHA_THRSHLD_00 = 56, ARC_PHA_THRSHLD_01 = 57, ARC_PHA_THRSHLD_02 = 58, ARC_PHA_THRSHLD_03 = 59, ARC_PHA_THRSHLD_04 = 60, ARC_PHA_THRSHLD_05 = 61, ARC_PHA_THRSHLD_06 = 62, ARC_PHA_THRSHLD_07 = 72, ARC_PHA_THRSHLD_08 = 73, ARC_PHA_THRSHLD_09 = 74, ARC_PHA_THRSHLD_10 = 75, ARC_PHA_THRSHLD_11 = 76, ARC_PHA_THRSHLD_12 = 77, ARC_PHA_THRSHLD_13 = 78, ARC_PHA_THRSHLD_14 = 88, ARC_PHA_THRSHLD_15 = 89, ARC_PHA_THRSHLD_16 = 90, ARC_PHA_THRSHLD_17 = 91, ARC_ADC_TACQ = 92, AFE_CONFIGURATION = 0, AFE_VETO_DAC = 1, AFE_VETO_VERNIER_DAC = 2, AFE_HLD_DAC = 3, AFE_BIAS_DAC = 4, AFE_TCI_DAC = 5, AFE_VERS_ADDR = 6, AFE_WRITE_CTR = 7, AFE_REJECT_CTR = 8, AFE_LOOP_CTR = 9, AFE_CHIP_ADDR = 10 } |
| Symbolic names for the registers of the LAT. | |
| enum | LEM_REG_BLK { CRU_BLK_CC = 0, EBM_BLK_CC = 0, EBM_BLK_STAT = 1, PDU_BLK_CC = 0, PDU_BLK_ENV = 1, GEM_BLK_CC = 0, GEM_BLK_TAM = 1, GEM_BLK_STAT = 2, GEM_BLK_SCHD = 3, GEM_BLK_ROI = 4, GEM_BLK_IE = 5, GEM_BLK_WIN = 6 } |
| Symbols for the register blocks. | |
| enum | LEM_DATA_LEN { CRU_DATA_LEN = 2, EBM_DATA_LEN = 2, GEM_DATA_LEN = 2, PDU_DATA_LEN = 2, TEM_DATA_LEN = 2, CCC_DATA_LEN = 2, CRC_DATA_LEN = 1, CFE_DATA_LEN = 1, TCC_DATA_LEN = 2, TRC_DATA_LEN = 4, TFE_DATA_LEN = 4, AEM_DATA_LEN = 2, ARC_DATA_LEN = 1, AFE_DATA_LEN = 1 } |
| Number of unsigned shorts in the data portion of a LATP packet. | |
| enum | LEM_CRU_MASK { CRU_MASK_TEM_0 = 0x00000001, CRU_MASK_TEM_1 = 0x00000002, CRU_MASK_TEM_2 = 0x00000004, CRU_MASK_TEM_3 = 0x00000008, CRU_MASK_TEM_4 = 0x00000010, CRU_MASK_TEM_5 = 0x00000020, CRU_MASK_TEM_6 = 0x00000040, CRU_MASK_TEM_7 = 0x00000080, CRU_MASK_TEM_8 = 0x00000100, CRU_MASK_TEM_9 = 0x00000200, CRU_MASK_TEM_A = 0x00000400, CRU_MASK_TEM_B = 0x00000800, CRU_MASK_TEM_C = 0x00001000, CRU_MASK_TEM_D = 0x00002000, CRU_MASK_TEM_E = 0x00004000, CRU_MASK_TEM_F = 0x00008000, CRU_MASK_TEM_ALL = 0x0000ffff, CRU_MASK_GEM = 0x00010000, CRU_MASK_AEM = 0x00020000, CRU_MASK_EBM = 0x00040000, CRU_MASK_PDU_0 = 0x00080000, CRU_MASK_PDU_1 = 0x00100000, CRU_MASK_PDU_ALL = 0x00180000, CRU_MASK_SIU_EXT = 0x01000000, CRU_MASK_SIU_0 = 0x02000000, CRU_MASK_SIU_1 = 0x04000000, CRU_MASK_SIU_ALL = 0x07000000, CRU_MASK_EPU_0 = 0x08000000, CRU_MASK_EPU_1 = 0x10000000, CRU_MASK_EPU_2 = 0x20000000, CRU_MASK_EPU_ALL = 0x38000000 } |
| Bit masks for the command and response enable registers of the CRU. | |
| enum | LEM_EBM_MASK { EBM_MASK_GEM = 0x00000001, EBM_MASK_TEM_0 = 0x00000002, EBM_MASK_TEM_1 = 0x00000004, EBM_MASK_TEM_2 = 0x00000008, EBM_MASK_TEM_3 = 0x00000010, EBM_MASK_TEM_4 = 0x00000020, EBM_MASK_TEM_5 = 0x00000040, EBM_MASK_TEM_6 = 0x00000080, EBM_MASK_TEM_7 = 0x00000100, EBM_MASK_TEM_8 = 0x00000200, EBM_MASK_TEM_9 = 0x00000400, EBM_MASK_TEM_A = 0x00000800, EBM_MASK_TEM_B = 0x00001000, EBM_MASK_TEM_C = 0x00002000, EBM_MASK_TEM_D = 0x00004000, EBM_MASK_TEM_E = 0x00008000, EBM_MASK_TEM_F = 0x00010000, EBM_MASK_AEM = 0x00020000, EBM_MASK_SIU_EXT = 0x00040000, EBM_MASK_SIU_0 = 0x00080000, EBM_MASK_SIU_1 = 0x00100000, EBM_MASK_EPU_0 = 0x00200000, EBM_MASK_EPU_1 = 0x00400000, EBM_MASK_EPU_2 = 0x00800000 } |
| Bit masks for the EBM input enables and output enables registers. | |
| enum | LEM_GEM_WIN_MASK { GEM_WIN_MASK_ROI = 0x01, GEM_WIN_MASK_TKR = 0x02, GEM_WIN_MASK_LOW = 0x04, GEM_WIN_MASK_HIGH = 0x08, GEM_WIN_MASK_CNO = 0x10, GEM_WIN_MASK_PERIOD = 0x20, GEM_WIN_MASK_SOLICIT = 0x40 } |
| Bit masks for the GEM window open mask register. | |
| enum | LEM_LOCAL_TYPE { TYPE_TEM_CC = 0, TYPE_TEM_TCC = 1, TYPE_TEM_CCC = 2, TYPE_TEM_TIC = 3, TYPE_AEM_CC = 0, TYPE_AEM_ENV = 1 } |
| TEM and AEM register block ids. | |
| enum | { LEM_MASTER = 0x20 } |
| Address bit indicating a master node. | |
| enum | LEM_LATP_ADDR { LEM_ADDR_TEM_0 = 0x00, LEM_ADDR_TEM_1 = 0x01, LEM_ADDR_TEM_2 = 0x02, LEM_ADDR_TEM_3 = 0x03, LEM_ADDR_TEM_4 = 0x04, LEM_ADDR_TEM_5 = 0x05, LEM_ADDR_TEM_6 = 0x06, LEM_ADDR_TEM_7 = 0x07, LEM_ADDR_TEM_8 = 0x08, LEM_ADDR_TEM_9 = 0x09, LEM_ADDR_TEM_A = 0x0a, LEM_ADDR_TEM_B = 0x0b, LEM_ADDR_TEM_C = 0x0c, LEM_ADDR_TEM_D = 0x0d, LEM_ADDR_TEM_E = 0x0e, LEM_ADDR_TEM_F = 0x0f, LEM_ADDR_GEM = 0x10, LEM_ADDR_AEM = 0x11, LEM_ADDR_EBM = 0x12, LEM_ADDR_PDU_0 = 0x13, LEM_ADDR_PDU_1 = 0x14, LEM_ADDR_CRU = 0x1E, LEM_ADDR_SLV_BCAST = 0x1F, LEM_ADDR_SIU_EXT = LEM_MASTER | 0x01, LEM_ADDR_SIU_0 = LEM_MASTER | 0x02, LEM_ADDR_SIU_1 = LEM_MASTER | 0x03, LEM_ADDR_EPU_0 = LEM_MASTER | 0x04, LEM_ADDR_EPU_1 = LEM_MASTER | 0x05, LEM_ADDR_EPU_2 = LEM_MASTER | 0x06, LEM_ADDR_MST_BCAST = LEM_MASTER | 0x1f } |
| Enumeration of LATp addresses. | |
| enum | { BCAST = 0x1F } |
| enum | LEM_PARITY_SELECT { LEM_PARITY_ODD = 0, LEM_PARITY_EVEN = 1 } |
| Options to the parity functions. More... | |
| enum | LEM_PARITY_TYPES { LEM_PARITY_CMD_STRING = 0, LEM_PARITY_CMD_PAYLOAD = 1, LEM_PARITY_ACCESS_DESC = 2 } |
| Types of parity that can be affected. More... | |
Functions | |
| static __inline unsigned long long | rotate_ (unsigned long long payload) |
| Switch the payload for the TFE DAC register between physical and logical. | |
$Id: defs.h,v 1.22 2011/03/25 18:51:52 apw Exp $
| enum LEM_PARITY_SELECT |
| enum LEM_PARITY_TYPES |
| static __inline unsigned long long rotate_ | ( | unsigned long long | payload | ) | [static] |
Switch the payload for the TFE DAC register between physical and logical.
| payload | The payload of the register load/read |
1.5.8