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GLAST / LAT > DAQ and FSW > FSW > Doxygen Index> LCBD / V1-5-1 > lcbb / mv2304

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LCB.h File Reference

Defines all the constants and public structures of the LCB. More...

#include "PBI/Endianness.h"

Classes
struct	_LCB_cmd_dsc_bf
	Map of LCB command (request,export) descriptor. More...
union	_LCB_cmd_dsc
	Union of the command (request, export) descriptor with an uninterpretted 32-bit integer. More...
struct	_LCB_rst_dsc_bfd
	Map of LCB result descriptor. More...
struct	_LCB_rst_dsc_bf
	Map of LCB result descriptor. More...
union	_LCB_rst_dsc
	union for 32-bit Result Descriptor More...
struct	_LCB_evt_dsc_bf
	Map of LCB event result descriptor with broken down status fields. More...
struct	_LCB_evt_dsc_bfe
	Map of LCB event result descriptor with error field as a single field (receive and transfer status combined). More...
union	_LCB_evt_dsc
	union for 32-bit Event Descriptor More...
struct	_LCB_prb
	Map of the LCB memory space PCI register block. More...
struct	_LCB_pci_csr_bf
	Map of the Memory space CSR pciister. More...
union	_LCB_pci_csr
	union for 32-bit CSR register More...
struct	_LCB_pci_irq_sets
	Map of the Memory space irq enable register, by sets. More...
struct	_LCB_pci_irq_bf
	Map of the Memory space irq register. More...
union	_LCB_pci_irq
	union for 32-bit irq register More...
struct	_LCB_pci_fabric_select_bf
	Bit field representation of the fabric select register. More...
struct	_LCB_pci_fabric_select
	Bit field representation of the fabric select register. More...
Defines
#define	LCB_PCI_VENDOR_ID   ( 0x11AA )
	16-bit PCI Vendor ID for LCB
#define	LCB_PCI_DEVICE_ID   ( 0x0845 )
	16-bit PCI Device ID for LCB
#define	LCB_RAD750_CACHELINE_SIZE   (1 << 5)
#define	LCB_RAD750_PREFETCH_SIZE   (6 * LCB_RAD750_CACHELINE_SIZE)
#define	LCB_REQUEST_LIST_ALIGN   (1 << 9)
	Necessary byte alignment for a request/command list.
#define	LCB_REQUEST_LIST_PAD   LCB_RAD750_PREFETCH_SIZE
	The size of the padding, in bytes, needed to ensure that request/ command list is protected against CPU accesses during the DMA operation.
#define	LCB_RESULT_LIST_ALIGN   LCB_RAD750_CACHELINE_SIZE
	Necessary byte alignment for a result list.
#define	LCB_RESULT_LIST_MIN   LCB_RAD750_PREFETCH_SIZE
	The minimum size, in bytes, needed to ensure that result list is protected against CPU accesses during the DMA operation.
#define	LCB_COMMAND_LIST_ALIGN   LCB_REQUEST_LIST_ALIGN
	Necessary byte alignment for a request/command list.
#define	LCB_COMMAND_LIST_PAD   LCB_REQUEST_LIST_PAD
	The size of the padding, in bytes, needed to ensure that request/ command list is protected against CPU accesses during the DMA operation.
#define	LCB_REQUEST_QUEUE_FULL   0xffffffff
	Value returned when the request queue is full, i.e. unable to accept a new request (command) list.
#define	LCB_REQUEST_QUEUE_NOT_EMPTY   0x00000000
	Value returned when the request queue is not empty, i.e. the request queue has outstanding transactions.
#define	LCB_RESULT_QUEUE_EMPTY   0xfffffff7
	Value returned when the result queue is read when empty.
#define	LCB_EVENT_QUEUE_EMPTY   0x7fffffff
	Value returned when the event queue is read when empty.
#define	LCB_REQUEST_LIST_MAX   (4088/sizeof(int))
	The maximum length, in 32-bit integers of a command list.
#define	LCB_EVT_PAYLOAD_MAX   (255*16)
	The maximum number of bytes that can be sent in a LCB-to-LCB transfer.
#define	LCB_EVENT_BUFFER_SIZE   ( 512 * 1024 )
	Size, in bytes, of the LCB event circular buffer.
#define	LCB_EVENT_BUFFER_GUARD   ( 128 * 1024 )
	Size, in bytes, of the LCB event circular buffer guard area.
#define	LCB_EVENT_BUFFER_TOTAL   (LCB_EVENT_BUFFER_SIZE+LCB_EVENT_BUFFER_GUARD)
	Size, in bytes, of the LCB event circular buffer + guard area.
#define	LCB_EVENT_BUFFER_ALIGN   ( 1 << 20 )
	Alignment factor, in bytes.
#define	LCB_EVT_PROTO_CNT   4
	Number of protocols supported by the event fabric.
#define	LCB_EVT_PAD_SIZE   32
	The size, in bytes, of the pad area left before each packet in the event ring buffer.
Typedefs
typedef enum _LCB_IRQ_COND	LCB_IRQ_COND
	Typedef for enum _LCB_IRQ_COND.
typedef enum _LCB_CMD_DSC_S	LCB_CMD_DSC_S
	Typedef for enum _LCB_CMD_DSC_S.
typedef enum _LCB_CMD_DSC_V	LCB_CMD_DSC_V
	Typedef for enum _LCB_CMD_DSC_V.
typedef enum _LCB_CMD_DSC_M	LCB_CMD_DSC_M
	Typedef for enum _LCB_CMD_DSC_M.
typedef struct _LCB_cmd_dsc_bf	LCB_cmd_dsc_bf
	Typedef of struct _LCB_cmd_dsc_bf.
typedef union _LCB_cmd_dsc	LCB_cmd_dsc
	Typedef for union _LCB_cmd_dsc.
typedef enum _LCB_RST_DSC_S	LCB_RST_DSC_S
	Typedef for enum _LCB_RST_DSC_S.
typedef enum _LCB_RST_DSC_V	LCB_RST_DSC_V
	Typedef for enum _LCB_RST_DSC_V.
typedef enum _LCB_RST_DSC_M	LCB_RST_DSC_M
	Typedef for enum _LCB_RST_DSC_M.
typedef struct _LCB_rst_dsc_bfd	LCB_rst_dsc_bfd
	Typedef for structure _LCB_rst_dsc_bfd.
typedef struct _LCB_rst_dsc_bf	LCB_rst_dsc_bf
	Typedef for structure _LCB_rst_dsc_bf.
typedef union _LCB_rst_dsc	LCB_rst_dsc
	typedef for union _LCB_rst_dsc
typedef enum _LCB_EVT_DSC_S	LCB_EVT_DSC_S
	Typedef for enum _LCB_EVT_DSC_S.
typedef enum _LCB_EVT_DSC_V	LCB_EVT_DSC_V
	Typedef for enum _LCB_EVT_DSC_V.
typedef enum _LCB_EVT_DSC_M	LCB_EVT_DSC_M
	Typedef for enum _LCB_EVT_DSC_M.
typedef struct _LCB_evt_dsc_bf	LCB_evt_dsc_bf
	typedef for struct _LCB_evt_dsc_bf
typedef struct _LCB_evt_dsc_bfe	LCB_evt_dsc_bfe
	typedef for struct _LCB_evt_dsc_bfe
typedef union _LCB_evt_dsc	LCB_evt_dsc
	typedef for union _LCB_evt_dsc
typedef enum _LCB_RST_ERR_XFR	LCB_RST_ERR_XFR
	Typedef for enum _LCB_RST_ERR_XFR.
typedef enum _LCB_RST_ERR_RCV	LCB_RST_ERR_RCV
	Typedef for enum _LCB_RST_ERR_RCV.
typedef enum _LCB_EVT_ERR_XFR	LCB_EVT_ERR_XFR
	Typedef for enum _LCB_EVT_ERR_XFR.
typedef enum _LCB_EVT_ERR_RCV	LCB_EVT_ERR_RCV
	Typedef for enum _LCB_EVT_ERR_RCV.
typedef struct _LCB_prb	LCB_prb
	Typedef for struct.
typedef enum _LCB_PCI_CSR_S	LCB_PCI_CSR_S
	Typedef for enum.
typedef enum _LCB_PCI_CSR_V	LCB_PCI_CSR_V
	Typedef for enum.
typedef enum _LCB_PCI_CSR_M	LCB_PCI_CSR_M
	Typedef for enum.
typedef enum _LCB_PCI_CSR_IRQEVTQUE_M	LCB_PCI_CSR_IRQEVTQUE_M
	Typedef for enum _LCB_PCI_IRQEVTQUE_M_.
typedef struct _LCB_pci_csr_bf	LCB_pci_csr_bf
	Typedef for struct.
typedef union _LCB_pci_csr	LCB_pci_csr
	typedef for union
typedef enum _LCB_IRQ_K	LCB_IRQ_K
	Typedef for the enum _LCB_IRQ_K.
typedef enum _LCB_IRQ_M	LCB_IRQ_M
	Typedef for the enum _LCB_IRQ_M.
typedef enum _LCB_PCI_IRQ_S	LCB_PCI_IRQ_S
	Typedef for enum _LCB_PCI_IRQ_S.
typedef enum _LCB_PCI_IRQ_V	LCB_PCI_IRQ_V
	Typedef for enum _LCB_PCI_IRQ_V.
typedef enum _LCB_PCI_IRQ_M	LCB_PCI_IRQ_M
	Typedef for enum _LCB_PCI_IRQ_M.
typedef struct _LCB_pci_irq_sets	LCB_pci_irq_sets
	Typedef for struct _LCB_pci_irq_sets.
typedef struct _LCB_pci_irq_bf	LCB_pci_irq_bf
	Typedef for struct _LCB_pci_irq_bf.
typedef union _LCB_pci_irq	LCB_pci_irq
	typedef for union _LCB_pci_irq
typedef enum _LCB_PCI_FABRIC_SELECT_PATH	LCB_PCI_FABRIC_SELECT_PATH
	Typedef for enum _LCB_PCI_FABRIC_SELECT_PATH.
typedef enum _LCB_PCI_FABRIC_SELECT_S	LCB_PCI_FABRIC_SELECT_S
	Typedef for enum _LCB_PCI_FABRIC_SELECT_S.
typedef enum _LCB_PCI_FABRIC_SELECT_V	LCB_PCI_FABRIC_SELECT_V
	Typedef for enum _LCB_PCI_FABRIC_SELECT_V.
typedef enum _LCB_PCI_FABRIC_SELECT_M	LCB_PCI_FABRIC_SELECT_M
	Typedef for enum _LCB_PCI_FABRIC_SELECT_M.
typedef struct _LCB_pci_fabric_select_bf	LCB_pci_fabric_select_bf
	Typedef for struct _LCB_pci_fabric_select_bf.
typedef struct _LCB_pci_fabric_select	LCB_pci_fabric_select
	Typedef for struct _LCB_pci_fabric_select.
Enumerations
enum	_LCB_IRQ_COND {   LCB_IRQ_COND_75_FULL = 0x0,   LCB_IRQ_COND_50_FULL = 0x1,   LCB_IRQ_COND_25_FULL = 0x2,   LCB_IRQ_COND_NOT_EMPTY = 0x3 }
	Enumerates the Interrupt Request conditions, both event buffer and event queue. More...
enum	_LCB_CMD_DSC_S {   LCB_CMD_DSC_S_LEN = 9,   LCB_CMD_DSC_S_ADR = 21 }
	Size, in bits, of the command descriptor fields. More...
enum	_LCB_CMD_DSC_V {   LCB_CMD_DSC_V_LEN = 0,   LCB_CMD_DSC_V_ADR = 9 }
	Right justified bit offsets of the command descriptor fields. More...
enum	_LCB_CMD_DSC_M {   LCB_CMD_DSC_M_LEN = 0x000001FF,   LCB_CMD_DSC_M_ADR = 0xFFFFFE00 }
	Masks of the command descriptor fields. More...
enum	_LCB_RST_DSC_S {   LCB_RST_DSC_S_STATUS = 3,   LCB_RST_DSC_S_DIR = 1,   LCB_RST_DSC_S_XSTATUS = 4,   LCB_RST_DSC_S_ADR = 28 }
	Size, in bits, of the result descriptor fields. More...
enum	_LCB_RST_DSC_V {   LCB_RST_DSC_V_STATUS = 0,   LCB_RST_DSC_V_XSTATUS = 0,   LCB_RST_DSC_V_DIR = 3,   LCB_RST_DSC_V_ADR = 4 }
	Right justified bit offsets of the result descriptor fields. More...
enum	_LCB_RST_DSC_M {   LCB_RST_DSC_M_STATUS = 0x00000007,   LCB_RST_DSC_M_DIR = 0x00000008,   LCB_RST_DSC_M_XSTATUS = 0x0000000F,   LCB_RST_DSC_M_ADR = 0xFFFFFFF0 }
	Masks of the result descriptor fields. More...
enum	_LCB_EVT_DSC_S {   LCB_EVT_DSC_S_OFFSET = 17,   LCB_EVT_DSC_S_LEN = 10,   LCB_EVT_DSC_S_STATUS = 5,   LCB_EVT_DSC_S_XSTATUS = 3,   LCB_EVT_DSC_S_RSTATUS = 2 }
	Size, in bits, of the event descriptor fields. More...
enum	_LCB_EVT_DSC_V {   LCB_EVT_DSC_V_OFFSET = 0,   LCB_EVT_DSC_V_LEN = 17,   LCB_EVT_DSC_V_STATUS = 27,   LCB_EVT_DSC_V_XSTATUS = 27,   LCB_EVT_DSC_V_RSTATUS = 30 }
	Right justified bit offsets of the event descriptor fields. More...
enum	_LCB_EVT_DSC_M {   LCB_EVT_DSC_M_OFFSET = 0x0001FFFF,   LCB_EVT_DSC_M_LEN = 0x07FE0000,   LCB_EVT_DSC_M_STATUS = 0xF8000000,   LCB_EVT_DSC_M_XSTATUS = 0x38000000,   LCB_EVT_DSC_M_RSTATUS = 0xC0000000 }
	Masks of the event descriptor fields. More...
enum	_LCB_RST_ERR_XFR {   LCB_RST_ERR_XFR_OUT_SUCCESS = 0,   LCB_RST_ERR_XFR_OUT_PCI_MASTER_ABORT = 1,   LCB_RST_ERR_XFR_OUT_PCI_PARITY_ERROR = 2,   LCB_RST_ERR_XFR_OUT_PCI_TARGET_ABORT = 3,   LCB_RST_ERR_XFR_OUT_UNDEFINED_4 = 4,   LCB_RST_ERR_XFR_OUT_BUFFER_EMPTY = 5,   LCB_RST_ERR_XFR_OUT_UNDEFINED_6 = 6,   LCB_RST_ERR_XFR_OUT_Q_EMPTY = 7,   LCB_RST_ERR_XFR_IN_SUCCESS = 8,   LCB_RST_ERR_XFR_IN_PCI_MASTER_ABORT = 9,   LCB_RST_ERR_XFR_IN_PCI_PARITY_ERROR = 10,   LCB_RST_ERR_XFR_IN_PCI_TARGET_ABORT = 11,   LCB_RST_ERR_XFR_IN_UNDEFINED_4 = 12,   LCB_RST_ERR_XFR_IN_UNDEFINED_5 = 13,   LCB_RST_ERR_XFR_IN_UNDEFINED_6 = 14,   LCB_RST_ERR_XFR_IN_UNDEFINED_7 = 15,   LCB_RST_ERR_XFR_CNT = 16 }
	Enumeration of possible LCB RESULT in/out errors. More...
enum	_LCB_RST_ERR_RCV {   LCB_RST_ERR_RCV_SUCCESS = 0,   LCB_RST_ERR_RCV_INVALID_HEADER_PARITY = 1,   LCB_RST_ERR_RCV_INVALID_DATA_PARITY = 2,   LCB_RST_ERR_RCV_UNDEFINED_3 = 3,   LCB_RST_ERR_RCV_TRANSMIT_UNDERRUN = 4,   LCB_RST_ERR_RCV_TIMEOUT = 5,   LCB_RST_ERR_RCV_INVALID_LIST = 6,   LCB_RST_ERR_RCV_UNDEFINED_7 = 7,   LCB_RST_ERR_RCV_CNT = 8 }
	Enumeration of possible LCB RESULT receive errors in result items. More...
enum	_LCB_EVT_ERR_XFR {   LCB_EVT_ERR_XFR_SUCCESS = 0,   LCB_EVT_ERR_XFR_PCI_MASTER_ABORT = 1,   LCB_EVT_ERR_XFR_PCI_PARITY_ERROR = 2,   LCB_EVT_ERR_XFR_PCI_TARGET_ABORT = 3,   LCB_EVT_ERR_XFR_UNDEFINED_4 = 4,   LCB_EVT_ERR_XFR_BUFFER_EMPTY = 5,   LCB_EVT_ERR_XFR_UNDEFINED_6 = 6,   LCB_EVT_ERR_XFR_Q_EMPTY = 7,   LCB_EVT_ERR_XFR_CNT = 8 }
	Enumeration of possible EVENT transfer errros. More...
enum	_LCB_EVT_ERR_RCV {   LCB_EVT_ERR_RCV_SUCCESS = 0,   LCB_EVT_ERR_RCV_UNDEFINED_1 = 1,   LCB_EVT_ERR_RCV_INVALID_DATA_PARITY = 2,   LCB_EVT_ERR_RCV_PACKET_TRUNCATED = 3,   LCB_EVT_ERR_RCV_CNT = 4 }
	Enumeration of possible LCB receive errors. More...
enum	_LCB_PCI_CSR_S {   LCB_PCI_CSR_S_INHBREQX = 1,   LCB_PCI_CSR_S_INHBRSTX = 1,   LCB_PCI_CSR_S_INHBEVTX = 1,   LCB_PCI_CSR_S_IRQEVTQUE = 2,   LCB_PCI_CSR_S_MBZ = 2,   LCB_PCI_CSR_S_CLK = 1,   LCB_PCI_CSR_S_UNUSED1 = 23,   LCB_PCI_CSR_S_LCB_RESET = 1 }
	Defines the size, in bits, for the various fields. More...
enum	_LCB_PCI_CSR_V {   LCB_PCI_CSR_V_INHBREQX = 0,   LCB_PCI_CSR_V_INHBRSTX = 1,   LCB_PCI_CSR_V_INHBEVTX = 2,   LCB_PCI_CSR_V_IRQEVTQUE = 3,   LCB_PCI_CSR_V_MBZ = 5,   LCB_PCI_CSR_V_CLK = 7,   LCB_PCI_CSR_V_UNUSED1 = 8,   LCB_PCI_CSR_V_LCB_RESET = 31 }
	Defines right shift amounts for the various fields. More...
enum	_LCB_PCI_CSR_M {   LCB_PCI_CSR_M_INHBREQX = 0x00000001,   LCB_PCI_CSR_M_INHBRSTX = 0x00000002,   LCB_PCI_CSR_M_INHBEVTX = 0x00000004,   LCB_PCI_CSR_M_IRQEVTQUE = 0x00000018,   LCB_PCI_CSR_M_MBZ = 0x00000060,   LCB_PCI_CSR_M_CLK = 0x00000080,   LCB_PCI_CSR_M_UNUSED1 = 0x7fffff00,   LCB_PCI_CSR_M_LCB_RESET = 0x80000000 }
	Defines bit masks for the various fields. More...
enum	_LCB_PCI_CSR_IRQEVTQUE_M {   LCB_PCI_CSR_IRQEVTQUE_M_COND_75_FULL,   LCB_PCI_CSR_IRQEVTQUE_M_COND_50_FULL,   LCB_PCI_CSR_IRQEVTQUE_M_COND_25_FULL,   LCB_PCI_CSR_IRQEVTQUE_M_COND_NOT_EMPTY }
	Enumerates the event buffer interrupt conditions as in place values. More...
enum	_LCB_IRQ_K {   LCB_IRQ_K_RESULT = 0,   LCB_IRQ_K_EVENT = 1,   LCB_IRQ_K_CLK_ON = 2,   LCB_IRQ_K_CLK_OFF = 3,   LCB_IRQ_K_SRC_CNT = 4 }
	Enumerates the 4 interrupt sources. More...
enum	_LCB_IRQ_M {   LCB_IRQ_M_RESULT = (1 << LCB_IRQ_K_RESULT),   LCB_IRQ_M_EVENT = (1 << LCB_IRQ_K_EVENT),   LCB_IRQ_M_CLK_ON = (1 << LCB_IRQ_K_CLK_ON),   LCB_IRQ_M_CLK_OFF = (1 << LCB_IRQ_K_CLK_OFF),   LCB_IRQ_M_CLKS }
	Enumerates the bit mask for the 4 interrupt sources. More...
enum	_LCB_PCI_IRQ_S {   LCB_PCI_IRQ_S_ENABLE = 4,   LCB_PCI_IRQ_S_ENABLE_RESULT = 1,   LCB_PCI_IRQ_S_ENABLE_EVENT = 1,   LCB_PCI_IRQ_S_ENABLE_CLK_ON = 1,   LCB_PCI_IRQ_S_ENABLE_CLK_OFF = 1,   LCB_PCI_IRQ_S_DISABLE = 4,   LCB_PCI_IRQ_S_DISABLE_RESULT = 1,   LCB_PCI_IRQ_S_DISABLE_EVENT = 1,   LCB_PCI_IRQ_S_DISABLE_CLK_ON = 1,   LCB_PCI_IRQ_S_DISABLE_CLK_OFF = 1,   LCB_PCI_IRQ_S_PENDING = 4,   LCB_PCI_IRQ_S_PENDING_RESULT = 1,   LCB_PCI_IRQ_S_PENDING_EVENT = 1,   LCB_PCI_IRQ_S_PENDING_CLK_ON = 1,   LCB_PCI_IRQ_S_PENDING_CLK_OFF = 1,   LCB_PCI_IRQ_S_CBUF = 4,   LCB_PCI_IRQ_S_CBUF_ENABLE = 1,   LCB_PCI_IRQ_S_CBUF_DISABLE = 1,   LCB_PCI_IRQ_S_CBUF_PENDING_BUF = 1,   LCB_PCI_IRQ_S_CBUF_PENDING_QUE = 1,   LCB_PCI_IRQ_S_UNUSED1 = 16 }
	Enumerates bit sizes of the IRQ enable/disable/pending fields. More...
enum	_LCB_PCI_IRQ_V {   LCB_PCI_IRQ_V_ENABLE = 0,   LCB_PCI_IRQ_V_ENABLE_RESULT = LCB_PCI_IRQ_V_ENABLE + LCB_IRQ_K_RESULT,   LCB_PCI_IRQ_V_ENABLE_EVENT = LCB_PCI_IRQ_V_ENABLE + LCB_IRQ_K_EVENT,   LCB_PCI_IRQ_V_ENABLE_CLK_ON = LCB_PCI_IRQ_V_ENABLE + LCB_IRQ_K_CLK_ON,   LCB_PCI_IRQ_V_ENABLE_CLK_OFF = LCB_PCI_IRQ_V_ENABLE + LCB_IRQ_K_CLK_OFF,   LCB_PCI_IRQ_V_DISABLE = 4,   LCB_PCI_IRQ_V_DISABLE_RESULT = LCB_PCI_IRQ_V_DISABLE + LCB_IRQ_K_RESULT,   LCB_PCI_IRQ_V_DISABLE_EVENT = LCB_PCI_IRQ_V_DISABLE + LCB_IRQ_K_EVENT,   LCB_PCI_IRQ_V_DISABLE_CLK_ON = LCB_PCI_IRQ_V_DISABLE + LCB_IRQ_K_CLK_ON,   LCB_PCI_IRQ_V_DISABLE_CLK_OFF = LCB_PCI_IRQ_V_DISABLE + LCB_IRQ_K_CLK_OFF,   LCB_PCI_IRQ_V_PENDING = 8,   LCB_PCI_IRQ_V_PENDING_RESULT = LCB_PCI_IRQ_V_PENDING + LCB_IRQ_K_RESULT,   LCB_PCI_IRQ_V_PENDING_EVENT = LCB_PCI_IRQ_V_PENDING + LCB_IRQ_K_EVENT,   LCB_PCI_IRQ_V_PENDING_CLK_ON = LCB_PCI_IRQ_V_PENDING + LCB_IRQ_K_CLK_ON,   LCB_PCI_IRQ_V_PENDING_CLK_OFF = LCB_PCI_IRQ_V_PENDING + LCB_IRQ_K_CLK_OFF,   LCB_PCI_IRQ_V_CBUF = 12,   LCB_PCI_IRQ_V_CBUF_ENABLE = 12,   LCB_PCI_IRQ_V_CBUF_DISABLE = 13,   LCB_PCI_IRQ_V_CBUF_PENDING_BUF = 14,   LCB_PCI_IRQ_V_CBUF_PENDING_QUE = 15,   LCB_PCI_IRQ_V_UNUSED1 = 16 }
	Enumerates right justified bit offsets the IRQ enable/disable/pending bits. More...
enum	_LCB_PCI_IRQ_M {   LCB_PCI_IRQ_M_ENABLE_RESULT = (1 << LCB_PCI_IRQ_V_ENABLE_RESULT),   LCB_PCI_IRQ_M_ENABLE_EVENT = (1 << LCB_PCI_IRQ_V_ENABLE_EVENT),   LCB_PCI_IRQ_M_ENABLE_CLK_ON = (1 << LCB_PCI_IRQ_V_ENABLE_CLK_ON),   LCB_PCI_IRQ_M_ENABLE_CLK_OFF = (1 << LCB_PCI_IRQ_V_ENABLE_CLK_OFF),   LCB_PCI_IRQ_M_ENABLE_QUES,   LCB_PCI_IRQ_M_ENABLE_CLKS,   LCB_PCI_IRQ_M_ENABLE_ALL,   LCB_PCI_IRQ_M_DISABLE_RESULT = (1 << LCB_PCI_IRQ_V_DISABLE_RESULT),   LCB_PCI_IRQ_M_DISABLE_EVENT = (1 << LCB_PCI_IRQ_V_DISABLE_EVENT),   LCB_PCI_IRQ_M_DISABLE_CLK_ON = (1 << LCB_PCI_IRQ_V_DISABLE_CLK_ON),   LCB_PCI_IRQ_M_DISABLE_CLK_OFF = (1 << LCB_PCI_IRQ_V_DISABLE_CLK_OFF),   LCB_PCI_IRQ_M_DISABLE_QUES,   LCB_PCI_IRQ_M_DISABLE_CLKS,   LCB_PCI_IRQ_M_DISABLE_ALL,   LCB_PCI_IRQ_M_PENDING_RESULT = (1 << LCB_PCI_IRQ_V_PENDING_RESULT),   LCB_PCI_IRQ_M_PENDING_EVENT = (1 << LCB_PCI_IRQ_V_PENDING_EVENT),   LCB_PCI_IRQ_M_PENDING_CLK_ON = (1 << LCB_PCI_IRQ_V_PENDING_CLK_ON),   LCB_PCI_IRQ_M_PENDING_CLK_OFF = (1 << LCB_PCI_IRQ_V_PENDING_CLK_OFF),   LCB_PCI_IRQ_M_PENDING_QUES,   LCB_PCI_IRQ_M_PENDING_CLKS,   LCB_PCI_IRQ_M_PENDING_ALL,   LCB_PCI_IRQ_M_CBUF_ENABLE = (1 << LCB_PCI_IRQ_V_CBUF_ENABLE),   LCB_PCI_IRQ_M_CBUF_DISABLE = (1 << LCB_PCI_IRQ_V_CBUF_DISABLE),   LCB_PCI_IRQ_M_CBUF_PENDING_BUF = (1 << LCB_PCI_IRQ_V_CBUF_PENDING_BUF),   LCB_PCI_IRQ_M_CBUF_PENDING_QUE = (1 << LCB_PCI_IRQ_V_CBUF_PENDING_QUE),   LCB_PCI_IRQ_M_CBUF,   LCB_PCI_IRQ_M_UNUSED1 = 0xffff0000 }
	Enumerates the IRQ enable/disable/pending bits. More...
enum	_LCB_PCI_FABRIC_SELECT_PATH {   LCB_PCI_FABRIC_SELECT_PATH_K_PRIMARY = 0,   LCB_PCI_FABRIC_SELECT_PATH_K_REDUNDANT = 1 }
	Enumerates the possible values of the path field in the fabric select register. More...
enum	_LCB_PCI_FABRIC_SELECT_S {   LCB_PCI_FABRIC_SELECT_S_PATH = 1,   LCB_PCI_FABRIC_SELECT_S_UNUSED = 31 }
	Enumerates the size, in bits, of the fields in the fabric select register. More...
enum	_LCB_PCI_FABRIC_SELECT_V {   LCB_PCI_FABRIC_SELECT_V_PATH = 0,   LCB_PCI_FABRIC_SELECT_V_UNUSED = 1 }
	Enumerates the right justified bit offsets of the fields in the fabric select register. More...
enum	_LCB_PCI_FABRIC_SELECT_M {   LCB_PCI_FABRIC_SELECT_M_PATH = (1 << LCB_PCI_FABRIC_SELECT_V_PATH),   LCB_PCI_FABRIC_SELECT_M_UNUSED = (0xFFFFFFFE) }
	Enumerates the mask field of the fields in the fabric select register. More...

---

Detailed Description

Defines all the constants and public structures of the LCB.

Author:

JJRussell - russell@slac.stanford.edu

   CVS $Id

INTRODUCTION

This file contains constants and LCB data structure that are useful to all clients of the LCB. Mostly these codify the various hardware definitions that the LCB package feels comfortable in exporting.

There are 4 major sections:

1. Miscellaneous Definitions
2. Definitions of the input and output descriptors
   • Request Descriptor, also called the Export Descriptor
   • Result Descriptor
   • Event Descriptor
3. Enumerations of the returned status codes from the
   • Result Descriptor, both out-bound and in-bound
   • Result Items
   • Event Descriptor, both transfer and receive
4. PCI side registers
   • PCI memory map
   • Register definitions

Conventions

All registers that are composed of non-trivial internal bit fields are represented as both

• C bit field structures
• A series of enumerations giving the
  • Field size, written as LCB_reg_S_component
  • Right justified bit field offset, written as LCB_reg_V_component
  • In place bit field mask, written as LCB_reg_M_component

where reg is the name of the register and component is the name of the component bit field. A union of the C bit field structures with a uninterpretted 32-bit integer is also defined, allowing easy conversion between the two representations.

---

Define Documentation

#define LCB_COMMAND_LIST_ALIGN   LCB_REQUEST_LIST_ALIGN

Necessary byte alignment for a request/command list.

This is a synomyn for LCB_REQUEST_ALIGN. In many places in the LCB software the request list is referred to as the command list.

#define LCB_COMMAND_LIST_PAD   LCB_REQUEST_LIST_PAD

The size of the padding, in bytes, needed to ensure that request/ command list is protected against CPU accesses during the DMA operation.

See also:

LCB_REQUEST_LIST_PAD

This is a synomyn for LCB_REQUEST_PAD. In many places in the LCB software the request list is referred to as the command list.

#define LCB_EVT_PAD_SIZE   32

The size, in bytes, of the pad area left before each packet in the event ring buffer.

The LCB hardware skips this number of bytes between the last message and the first byte of the incoming message. This pad area is provided for the consumer (either driver or end user) to use to store contextual information. The intent is to save the consumer from allocating yet another piece of memory for this purpose.

#define LCB_EVT_PAYLOAD_MAX   (255*16)

The maximum number of bytes that can be sent in a LCB-to-LCB transfer.

The transfer is always in units of an integer number of LATp cells which are 16 bytes. The LCB can transfer a max of 255 LATp cells. This number is defined as the maximum size of the payload. The definition of the payload includes the 2 bytes used for the mandatory LATp header. Said another way, the maximum size of user part of the payload is this number less the 2 bytes for the LATp header.

#define LCB_EVT_PROTO_CNT   4

Number of protocols supported by the event fabric.

When sending of receiving data on the event fabric, the data packet always contains a 16-bit LATp cell header word. Within this header word resides a two bits protocol field. The receiving LATp node may use this protocol field to aid in determining the nature of the nature. If the receiving node is a CPU, then the software may chose to use the protocol field to route the data packet to the proper handler. In the case where the receiving node is the Event Builder, the protocol field determines whether to build the event or to simple pass it on to its LATp destination addres.

#define LCB_REQUEST_LIST_MAX   (4088/sizeof(int))

The maximum length, in 32-bit integers of a command list.

This number can be as large as 4088 + 4. This is from the LCB specification V4.0, LAT-TD-00860-01.

#define LCB_REQUEST_LIST_PAD   LCB_RAD750_PREFETCH_SIZE

The size of the padding, in bytes, needed to ensure that request/ command list is protected against CPU accesses during the DMA operation.

If the CPU addesses a memory location in the same cache line that the bridge chip is accessing with a read operation, the RAD750's bridge will hang. Given that the bridge chip can prefetch as many as 6 cache lines, one way to protect against this is to always ensure that the request list always is extended by the prefetch buffer size.

#define LCB_RESULT_LIST_MIN   LCB_RAD750_PREFETCH_SIZE

The minimum size, in bytes, needed to ensure that result list is protected against CPU accesses during the DMA operation.

If the CPU addesses a memory location in the same cache line that the bridge chip is accessing with a read operation, the RAD750's bridge will hang. Given that the bridge chip can prefetch as many as 6 cache lines, one way to protect against this is to always ensure that the result list is at least 6 cache lines in length.

Note:

The protection here is different from the protection on the command list. The result list is being DMA'd into the CPU, i.e. a write operation, so, since the protection is only needed on read accesses, this portion of the transfer need not be protected. However, to flush a potentially only partially filled cache line in the bridge chip, the LCB performs a read operation on the first location in the result list. This is where a potential collision could occur. If the result list is shorter than the bridge chip's prefetch buffer, the CPU could have legitimate data structures in this area immediately after the result list. By ensuring that the result list has a minimum length of this prefetch size, the CPU should have no legitimate need to access memory in this unsafe zone.

---

Typedef Documentation

LCB_EVT_ERR_XFR

Typedef for enum _LCB_EVT_ERR_XFR.

PCI Master Abort

This is likely due to a bad DMA destination address. In this case, typically there is no data transferred, but one is still obligated to free the padding area and, if any, the number of words specified by the length, although, again, this is almost certainly going to be 0.

PCI Parity Error

PCI Parity Error occurs only on reads. Since this is a write operation, this error should not occur

PCI Target Abort

This error is a little iffer in origin, but a bad address is a good candidate. The difference between this and a PCI Master Abort is that in the Master Abort, no one responded to the memory address. In this operation, the operation is rejected (like trying to write into read only memory). Basically, the operation being requested is not in the target's side repertorie.

Buffer Empty

This is an internal underflow situation where the descriptor claims so many words are available, but the FIFO runs dry before that. This is internal hardware inconsistency and is a design fault. The data fill have the last legitimate word duplicated until the requisite number of words (as claimed by the result descriptor) is exhausted. There is no way for the user to absolutely known where the last good word occcurred.

Empty

This is perfectly normal and occurs when the event descriptor que has run out.

LCB_IRQ_K

Typedef for the enum _LCB_IRQ_K.

The LCB is capable of delivering interrupts from 4 different sources,

• The result queue
• The event queue
• The clock transiting from on to off
• The clock transiting from off to on

At any given time, one and only one of the clock transition interrupts will be active, except possibly at initialization time. It is considered an error for both to be inactive or active at the same time.

There are three set of status bits associated with these interrupts

• The set of enabled interrupts
• The set of disabled interrupts
• The set of pending interrupts

Only enabled and pending interrupts result in an interrupt being delivered to the CPU. The set of enabled and disabled interrupts is mutually exclusive, i.e. it is considered an error for a particular interrupt to be either both enabled and disabled or to be neither enabled or disabled.

This enumeration gives the offset of each interrupt within the sets.

Note:

There is a fourth set of bits that does not follow this pattern. This set contains bits that control and give the status of the two sources that feed the event interrupt, the buffer full condition and the event queue highwater mark exceeded condition. See LCB_pci_irq_bf for details.

LCB_pci_csr

typedef for union

See also:

_LCB_pci_csr

LCB_pci_csr_bf

Typedef for struct.

See also:

_LCB_pci_csr_bf

LCB_PCI_CSR_M

Typedef for enum.

See also:

_LCB_PCI_CSR_M

LCB_PCI_CSR_S

Typedef for enum.

See also:

_LCB_PCI_CSR_S;

LCB_PCI_CSR_V

Typedef for enum.

See also:

_LCB_PCI_CSR_V

LCB_PCI_FABRIC_SELECT_PATH

Typedef for enum _LCB_PCI_FABRIC_SELECT_PATH.

This enumerates the possible value of the path field in the fabric select register. Currently only 1 bit is defined.

LCB_pci_irq_bf

Typedef for struct _LCB_pci_irq_bf.

The interrupt enable register consists of 3 sets of 4 bits. The 4 bits are:

1. 1 bit for the result interrupts
2. 1 bit for the event interrupts
3. 1 bit for the clock on interrupt (fires on transition of off->on)
4. 1 bit for the clock off interrupt (fires on transition of on->off)

The three sets represent

1. Enable the interrupt
2. Disable the interrupt
3. State of the interrupt (read-only)

It is illegal to simoultaneously request the same interrupt to be both enable and disabled.

Circular Buffer Set

There is a fourth set of bits that does not follow this pattern. This set contains bits that control and give

1. Enable buffer full as a contributor to the event interrupt
2. Disable buffer full as a contributor to the event interrupt
3. Buffer full condition meet
4. Queue highwater mark condition meet.

Note:

There is not a separate enable for the Que highwater mark condition. This was felt to be redundant with the ability to enable/disable the global event interrupt.

LCB_PCI_IRQ_M

Typedef for enum _LCB_PCI_IRQ_M.

The interrupt enable register consists of 3 sets of 4 bits. The 4 bits are:

1. 1 bit for the result interrupts
2. 1 bit for the event interrupts
3. 1 bit for the clock on interrupt (fires on transition of off->on)
4. 1 bit for the clock off interrupt (fires on transition of on->off)

The three sets represent

1. Enable the interrupt (on write, on read enable(1)/disable(0) status
2. Disable the interrupt (on write, on read, mbz
3. State of the interrupt (read-only)

It is illegal to simoultaneously request the same interrupt to be both enable and disabled. The enable/dis

There is now a fourth set controlling and giving the status of the interrupts associated with the circular buffer. This set of four bits is

1. Enable the circular buffer full interrupt (on write, on read enable(1)/disable(1) status
2. Disable the circular buffer full interrupt (on write, on read, mbz)
3. Circular buffer full interrupt pending (read-only)
4. Circular que interrupt pending (read-only)

Note:

The convenience definitions, e.g. LCB_PCI_IRQ_M_ENABLE_ALL do not include the circular buffer condition

Circular Buffer Set

There is a fourth set of bits that does not follow this pattern. This set contains bits that control and give the status of the two sources that feed the event interrupt, the buffer full condition and the event queue highwater mark exceeded condition. See LCB_pci_irq_bf for details.

LCB_PCI_IRQ_S

Typedef for enum _LCB_PCI_IRQ_S.

The interrupt enable register consists of 3 sets of 4 bits. The 4 bits are:

1. 1 bit for the result interrupts
2. 1 bit for the event interrupts
3. 1 bit for the clock on interrupt (fires on transition of off->on)
4. 1 bit for the clock off interrupt (fires on transition of on->off)

The three sets represent

1. Enable the interrupt
2. Disable the interrupt
3. State of the interrupt (read-only)

It is illegal to simoultaneously request the same interrupt to be both enable and disabled.

Circular Buffer Set

There is a fourth set of bits that does not follow this pattern. This set contains bits that control and give the status of the two sources that feed the event interrupt, the buffer full condition and the event queue highwater mark exceeded condition. See LCB_pci_irq_bf for details.

LCB_pci_irq_sets

Typedef for struct _LCB_pci_irq_sets.

The interrupt enable register consists of 3 sets of 4 bits. The 4 bits are:

1. 1 bit for the result interrupts
2. 1 bit for the event interrupts
3. 1 bit for the clock on interrupt (fires on transition of off->on)
4. 1 bit for the clock off interrupt (fires on transition of on->off)

The three sets represent

1. Enable the interrupt
2. Disable the interrupt
3. State of the interrupt (read-only)

It is illegal to simoultaneously request the same interrupt to be both enable and disabled.

Circular Buffer Set

There is a fourth set of bits that does not follow this pattern. This set contains bits that control and give the status of the two sources that feed the event interrupt, the buffer full condition and the event queue highwater mark exceeded condition. See LCB_pci_irq_bf for details.

LCB_PCI_IRQ_V

Typedef for enum _LCB_PCI_IRQ_V.

The interrupt enable register consists of 3 sets of 4 bits. The 4 bits are:

1. 1 bit for the result interrupts
2. 1 bit for the event interrupts
3. 1 bit for the clock on interrupt (fires on transition of off->on)
4. 1 bit for the clock off interrupt (fires on transition of on->off)

The three sets represent

1. Enable the interrupt
2. Disable the interrupt
3. State of the interrupt (read-only)

It is illegal to simoultaneously request the same interrupt to be both enable and disabled.

Circular Buffer Set

There is a fourth set of bits that does not follow this pattern. This set contains bits that control and give the status of the two sources that feed the event interrupt, the buffer full condition and the event queue highwater mark exceeded condition. See LCB_pci_irq_bf for details.

LCB_prb

Typedef for struct.

See also:

_LCB_prb

The definitive source for the register map is LAT-TD-860-01, section 2.2 The names where chosen to follow as closely as possible the names used in the document.

LCB_rst_dsc

typedef for union _LCB_rst_dsc

About this Representation

This representation of the result descriptor is a union of 3 different representations,

• LCB_rst_dsc_bfd,
• LCB_rst_dsc_bf
• An unsigned 32-bit integer.

Each has its use, with the use of e LCB_rst_dsc_bfd and LCB_rst_bf documented in their respective sections. The result descriptor as a 32-bit integer is encouraged when coping passing the result descriptor and when passing the result descriptor by value. Note that when passing unions in as parameters, the GCC compiler chooses to pass by address.

LCB_rst_dsc_bf

Typedef for structure _LCB_rst_dsc_bf.

Treatment of the Direction/Status Fields

This representatin of the result descriptor treats the direction and @ status field as a single field, called the transfer status field, xstatus. This representation is convenient, for example, when performing statistics on the fate of the transaction or when capturing the value of this two fields.

See also:

LCB_rst_dsc_bfd This representation treats the direction field and status fields as two distinct fields and may be more useful when trying to interpret the meaning of the PCI address field.

LCB_rst_dsc_bfd

Typedef for structure _LCB_rst_dsc_bfd.

Treatment of the Direction/Status Fields

This structure maps out the bit fields of the result descriptor in a representation that separates the direction field from the status field. The interpretation of both the status field and the adr field is dependent of the value of the dir field.

Interpretation of the Status Field

The direction bit determines if the status field. is interpretted as an in-bound status of out-bound status. If the direction bit is clear (0), then status represents an out-bound status, if set (1), then status represents an in-bound status. In both cases, if the status field is clear (0), then the transaction completed successfully.

Interpretation of the Address Field

The direction bit determines if the address field is a "result list" address or a "request list" address. If the direction bit is clear (0), then adr represents the PCI address of the result-list, if set (1), then adr represents the PCI address of the request-list.

See also:

LCB_rst_dsc_bf This representation treats the direction an status fields as a single field and may be more convenient for doing statistics on this field or capturing the value of these two fields.

---

Enumeration Type Documentation

enum _LCB_CMD_DSC_M

Masks of the command descriptor fields.

Enumerator:

LCB_CMD_DSC_M_LEN	Transaction field bit field mask
LCB_CMD_DSC_M_ADR	PCI address field bit field mask

enum _LCB_CMD_DSC_S

Size, in bits, of the command descriptor fields.

Enumerator:

LCB_CMD_DSC_S_LEN	Transaction field, bit field size
LCB_CMD_DSC_S_ADR	PCI address field, bit field size

enum _LCB_CMD_DSC_V

Right justified bit offsets of the command descriptor fields.

Enumerator:

LCB_CMD_DSC_V_LEN	Transaction field, bit field offset
LCB_CMD_DSC_V_ADR	PCI address field, bit field offset

enum _LCB_EVT_DSC_M

Masks of the event descriptor fields.

Enumerator:

LCB_EVT_DSC_M_OFFSET	Circular buffer offset, mask
LCB_EVT_DSC_M_LEN	Size of the event in units of 32-bit words, bit field mask
LCB_EVT_DSC_M_STATUS	Combined status, bit field mask
LCB_EVT_DSC_M_XSTATUS	Transfer status, bit field mask
LCB_EVT_DSC_M_RSTATUS	Receive status, bit field mask

enum _LCB_EVT_DSC_S

Size, in bits, of the event descriptor fields.

Enumerator:

LCB_EVT_DSC_S_OFFSET	Circular buffer offset, size in bits
LCB_EVT_DSC_S_LEN	Size of the event in units of 32-bit words, size in bits
LCB_EVT_DSC_S_STATUS	Combined status, size in bits
LCB_EVT_DSC_S_XSTATUS	Transfer status, size in bits
LCB_EVT_DSC_S_RSTATUS	Receive status, size in bits

enum _LCB_EVT_DSC_V

Right justified bit offsets of the event descriptor fields.

Enumerator:

LCB_EVT_DSC_V_OFFSET	Circular buffer offset, bit field offset
LCB_EVT_DSC_V_LEN	Size of the event in units of 32-bit words, bit field offset
LCB_EVT_DSC_V_STATUS	Combined status, bit field offset
LCB_EVT_DSC_V_XSTATUS	Transfer status, bit field offset
LCB_EVT_DSC_V_RSTATUS	Receive status, bit field offset

enum _LCB_EVT_ERR_RCV

Enumeration of possible LCB receive errors.

These are errors that the LCB detects when accepting data from a LATp event fabric. These map the 2-bit field in event descriptor.

Enumerator:

LCB_EVT_ERR_RCV_SUCCESS	LATp success
LCB_EVT_ERR_RCV_UNDEFINED_1	Undefined error #1
LCB_EVT_ERR_RCV_INVALID_DATA_PARITY	LATp data parity error
LCB_EVT_ERR_RCV_PACKET_TRUNCATED	LATp packet truncated error
LCB_EVT_ERR_RCV_CNT	Count of these error types

enum _LCB_EVT_ERR_XFR

Enumeration of possible EVENT transfer errros.

These errors occur when the LCB transfers data across the PCI bus into the circular buffer.

Enumerator:

LCB_EVT_ERR_XFR_SUCCESS	Transfer okay
LCB_EVT_ERR_XFR_PCI_MASTER_ABORT	PCI Master Abort error
LCB_EVT_ERR_XFR_PCI_PARITY_ERROR	PCI Parity Error,NOT REPORTED
LCB_EVT_ERR_XFR_PCI_TARGET_ABORT	PCI Target Abort error
LCB_EVT_ERR_XFR_UNDEFINED_4	PCI Stop asserted, DEFUNCT
LCB_EVT_ERR_XFR_BUFFER_EMPTY	Undefined error #4
LCB_EVT_ERR_XFR_UNDEFINED_6	Insufficient memory, DEFUNCT
LCB_EVT_ERR_XFR_Q_EMPTY	Undefined error #6
LCB_EVT_ERR_XFR_CNT	Count of RESULT in errors

enum _LCB_IRQ_COND

Enumerates the Interrupt Request conditions, both event buffer and event queue.

Enumerator:

LCB_IRQ_COND_75_FULL	Interrupt condition -- 75% full
LCB_IRQ_COND_50_FULL	Interrupt condition -- 50% full
LCB_IRQ_COND_25_FULL	Interrupt condition -- 25% full
LCB_IRQ_COND_NOT_EMPTY	Interrupt condition -- NOT empty

enum _LCB_IRQ_K

Enumerates the 4 interrupt sources.

Enumerator:

LCB_IRQ_K_RESULT	The interrupt associated with the result que
LCB_IRQ_K_EVENT	The interrupt associated with the event que
LCB_IRQ_K_CLK_ON	The interrupt associated with the clock off -> on tranistion
LCB_IRQ_K_CLK_OFF	The interrupt associated with the clock on -> off, tranistion
LCB_IRQ_K_SRC_CNT	The number of interrupt sources

enum _LCB_IRQ_M

Enumerates the bit mask for the 4 interrupt sources.

Enumerator:

LCB_IRQ_M_RESULT	Bit mask for result
LCB_IRQ_M_EVENT	Bit mask for event
LCB_IRQ_M_CLK_ON	Bit mask for clock on
LCB_IRQ_M_CLK_OFF	Bit mask for clock off
LCB_IRQ_M_CLKS	Bit mask for both clock on and clock off

enum _LCB_PCI_CSR_IRQEVTQUE_M

Enumerates the event buffer interrupt conditions as in place values.

Enumerator:

LCB_PCI_CSR_IRQEVTQUE_M_COND_75_FULL	Interrupt when event queue is at least 75% full
LCB_PCI_CSR_IRQEVTQUE_M_COND_50_FULL	Interrupt when event queue is at least 50% full
LCB_PCI_CSR_IRQEVTQUE_M_COND_25_FULL	Interrupt when event queue is at least 75% full
LCB_PCI_CSR_IRQEVTQUE_M_COND_NOT_EMPTY	Interrupt when event queue is not empty

enum _LCB_PCI_CSR_M

Defines bit masks for the various fields.

Enumerator:

LCB_PCI_CSR_M_INHBREQX	Inhibit request transfer, testing only
LCB_PCI_CSR_M_INHBRSTX	Inhibit result transfer, testing only
LCB_PCI_CSR_M_INHBEVTX	Inhibit event transfer, testing only
LCB_PCI_CSR_M_IRQEVTQUE	Event queue interrupt condition
LCB_PCI_CSR_M_MBZ	Former Event buffer interrupt condition, now MBZ
LCB_PCI_CSR_M_CLK	Clock present, read-only
LCB_PCI_CSR_M_UNUSED1	Unused -- must be zero
LCB_PCI_CSR_M_LCB_RESET	Initiate a reset of the LCB itself

enum _LCB_PCI_CSR_S

Defines the size, in bits, for the various fields.

;

Enumerator:

LCB_PCI_CSR_S_INHBREQX	Inhibit request transfer,testing only
LCB_PCI_CSR_S_INHBRSTX	Inhibit result transfer, testing only
LCB_PCI_CSR_S_INHBEVTX	Inhibit event transfer, testing only
LCB_PCI_CSR_S_IRQEVTQUE	event queue interrupt condition
LCB_PCI_CSR_S_MBZ	former event buffer interrupt condition, now MBZ
LCB_PCI_CSR_S_CLK	Clock present, read-only
LCB_PCI_CSR_S_UNUSED1	Unused -- must be zero
LCB_PCI_CSR_S_LCB_RESET	Initiate a reset of the LCB itself

enum _LCB_PCI_CSR_V

Defines right shift amounts for the various fields.

Enumerator:

LCB_PCI_CSR_V_INHBREQX	Inhibit request transfer,testing only
LCB_PCI_CSR_V_INHBRSTX	Inhibit result transfer,testing only
LCB_PCI_CSR_V_INHBEVTX	Inhibit event transfer, testing only
LCB_PCI_CSR_V_IRQEVTQUE	event queue interrupt condition
LCB_PCI_CSR_V_MBZ	former event buffer interrupt condition now mbz
LCB_PCI_CSR_V_CLK	Clock present, read-only
LCB_PCI_CSR_V_UNUSED1	Unused -- must be zero
LCB_PCI_CSR_V_LCB_RESET	Initiate a reset of the LCB itself

enum _LCB_PCI_FABRIC_SELECT_M

Enumerates the mask field of the fields in the fabric select register.

Enumerator:

LCB_PCI_FABRIC_SELECT_M_PATH	Path field, mask
LCB_PCI_FABRIC_SELECT_M_UNUSED	Unused field, mask

enum _LCB_PCI_FABRIC_SELECT_PATH

Enumerates the possible values of the path field in the fabric select register.

Enumerator:

LCB_PCI_FABRIC_SELECT_PATH_K_PRIMARY	Use primary path
LCB_PCI_FABRIC_SELECT_PATH_K_REDUNDANT	Use redundant path

enum _LCB_PCI_FABRIC_SELECT_S

Enumerates the size, in bits, of the fields in the fabric select register.

Enumerator:

LCB_PCI_FABRIC_SELECT_S_PATH	Path size, in bits
LCB_PCI_FABRIC_SELECT_S_UNUSED	Unused size, in bits, MBZ

enum _LCB_PCI_FABRIC_SELECT_V

Enumerates the right justified bit offsets of the fields in the fabric select register.

Enumerator:

LCB_PCI_FABRIC_SELECT_V_PATH	Path size, in bits
LCB_PCI_FABRIC_SELECT_V_UNUSED	Unused size, in bits, MBZ

enum _LCB_PCI_IRQ_M

Enumerates the IRQ enable/disable/pending bits.

Enumerator:

LCB_PCI_IRQ_M_ENABLE_RESULT	Enable the result interrupt, mask field
LCB_PCI_IRQ_M_ENABLE_EVENT	Enable the event interrupt, mask field
LCB_PCI_IRQ_M_ENABLE_CLK_ON	Enable the clock on interrupt, mask field
LCB_PCI_IRQ_M_ENABLE_CLK_OFF	Enable the clock off interrupt, mask field
LCB_PCI_IRQ_M_ENABLE_CLKS	Enable both result and event interrupts
LCB_PCI_IRQ_M_ENABLE_ALL	Enable both clock on and clock off interrupts
LCB_PCI_IRQ_M_DISABLE_RESULT	Enable all the interrupts, mask field Disable the result interrupt, mask field
LCB_PCI_IRQ_M_DISABLE_EVENT	Disable the event interrupt, mask field
LCB_PCI_IRQ_M_DISABLE_CLK_ON	Disable the clock on interrupt, mask field
LCB_PCI_IRQ_M_DISABLE_CLK_OFF	Disable the clock off interrupt, mask field
LCB_PCI_IRQ_M_DISABLE_CLKS	Disable both the result and event interrupts
LCB_PCI_IRQ_M_DISABLE_ALL	Enable both clock on and clock off interrupts
LCB_PCI_IRQ_M_PENDING_RESULT	Enable all the interrupts, mask field Result pending, read-only, mask field
LCB_PCI_IRQ_M_PENDING_EVENT	Event pending, read-only, mask field
LCB_PCI_IRQ_M_PENDING_CLK_ON	Clock on pending, read-only, mask field
LCB_PCI_IRQ_M_PENDING_CLK_OFF	Clock off pending, read-only, mask field
LCB_PCI_IRQ_M_PENDING_QUES	State of both result and event pending bits, read-only, mask field
LCB_PCI_IRQ_M_PENDING_ALL	State of both clock on and clock off pending bits, read-only mask field
LCB_PCI_IRQ_M_CBUF_ENABLE	State of all the pending bits, read-only, mask field Enable the circular buffer full interrupt, on write; on read 0 = disabled, 1 = enabled
LCB_PCI_IRQ_M_CBUF_DISABLE	Disable the circular buffer full interrupt, on write; on read, mbz
LCB_PCI_IRQ_M_CBUF_PENDING_BUF	State of interrupt of circular buffer full condition (read-only)
LCB_PCI_IRQ_M_CBUF_PENDING_QUE	State of interrupt of circular queue condition (read-only)
LCB_PCI_IRQ_M_CBUF	Mask for the circular buffer set
LCB_PCI_IRQ_M_UNUSED1	Unused, mbz

enum _LCB_PCI_IRQ_S

Enumerates bit sizes of the IRQ enable/disable/pending fields.

Enumerator:

LCB_PCI_IRQ_S_ENABLE	Enable field size, in bits
LCB_PCI_IRQ_S_ENABLE_RESULT	Enable the result interrupt, size
LCB_PCI_IRQ_S_ENABLE_EVENT	Enable the event interrupt, size
LCB_PCI_IRQ_S_ENABLE_CLK_ON	Enable clock on interrupt, size
LCB_PCI_IRQ_S_ENABLE_CLK_OFF	Enable clock off interrupt, size
LCB_PCI_IRQ_S_DISABLE	Disable field size, in bits
LCB_PCI_IRQ_S_DISABLE_RESULT	Disable the result interrupt, size
LCB_PCI_IRQ_S_DISABLE_EVENT	Disable the event interrupt, size
LCB_PCI_IRQ_S_DISABLE_CLK_ON	Disable clock on interrupt, size
LCB_PCI_IRQ_S_DISABLE_CLK_OFF	Disable clock off interrupt, size
LCB_PCI_IRQ_S_PENDING	Pending field size, in bits,
LCB_PCI_IRQ_S_PENDING_RESULT	Result pending, read-only, size
LCB_PCI_IRQ_S_PENDING_EVENT	Event pending, read-only, size
LCB_PCI_IRQ_S_PENDING_CLK_ON	Clock on pending interrupt, size
LCB_PCI_IRQ_S_PENDING_CLK_OFF	Clock off pending interrupt, size
LCB_PCI_IRQ_S_CBUF	Circular buffer status size, in bits
LCB_PCI_IRQ_S_CBUF_ENABLE	Circular buffer enable (on write) on read, 0= disabled 1= enabled
LCB_PCI_IRQ_S_CBUF_DISABLE	Circular buffer disable (on write) on read, mbz
LCB_PCI_IRQ_S_CBUF_PENDING_BUF	Circular buffer pending, readonly
LCB_PCI_IRQ_S_CBUF_PENDING_QUE	Circular queue pending, readonly
LCB_PCI_IRQ_S_UNUSED1	Unused, mbz

enum _LCB_PCI_IRQ_V

Enumerates right justified bit offsets the IRQ enable/disable/pending bits.

Enumerator:

LCB_PCI_IRQ_V_ENABLE	Enable field offset
LCB_PCI_IRQ_V_ENABLE_RESULT	Enable the result interrupt, offset
LCB_PCI_IRQ_V_ENABLE_EVENT	Enable the event interrupt, offset
LCB_PCI_IRQ_V_ENABLE_CLK_ON	Enable the clock on interrupt,offset
LCB_PCI_IRQ_V_ENABLE_CLK_OFF	Enable the clock off interrupt,offset
LCB_PCI_IRQ_V_DISABLE	Disable field offset
LCB_PCI_IRQ_V_DISABLE_RESULT	Disable the result interrupt, offset
LCB_PCI_IRQ_V_DISABLE_EVENT	Disable the event interrupt, offset
LCB_PCI_IRQ_V_DISABLE_CLK_ON	Disable the clock on interrupt,offset
LCB_PCI_IRQ_V_DISABLE_CLK_OFF	Disable the clock off interrupt,offset
LCB_PCI_IRQ_V_PENDING	Pending field offset
LCB_PCI_IRQ_V_PENDING_RESULT	Result pending, read-only, offset
LCB_PCI_IRQ_V_PENDING_EVENT	Event pending, read-only, offset
LCB_PCI_IRQ_V_PENDING_CLK_ON	Clock on pending, read-only, offset
LCB_PCI_IRQ_V_PENDING_CLK_OFF	Clock off pending, read-only, offset
LCB_PCI_IRQ_V_CBUF	Circular buffer field offset
LCB_PCI_IRQ_V_CBUF_ENABLE	Circular buffer enable (on write) on read, 0= disabled 1= enabled
LCB_PCI_IRQ_V_CBUF_DISABLE	Circular buffer disable (on write) on read, mbz
LCB_PCI_IRQ_V_CBUF_PENDING_BUF	Circular buffer interrupt pending, readonly
LCB_PCI_IRQ_V_CBUF_PENDING_QUE	Circular queue interrupt pending, readonly
LCB_PCI_IRQ_V_UNUSED1	Unused, mbz

enum _LCB_RST_DSC_M

Masks of the result descriptor fields.

Enumerator:

LCB_RST_DSC_M_STATUS	Transfer status only, bit field mask
LCB_RST_DSC_M_DIR	Direction only, bit field mask
LCB_RST_DSC_M_XSTATUS	Transfer status + direction
LCB_RST_DSC_M_ADR	PCI address field, bit field mask

enum _LCB_RST_DSC_S

Size, in bits, of the result descriptor fields.

Enumerator:

LCB_RST_DSC_S_STATUS	Transfer status field only, bit field size
LCB_RST_DSC_S_DIR	Transfer direction, bit field size
LCB_RST_DSC_S_XSTATUS	Transfer status field + direction, bit field size
LCB_RST_DSC_S_ADR	PCI address field, bit field size

enum _LCB_RST_DSC_V

Right justified bit offsets of the result descriptor fields.

Enumerator:

LCB_RST_DSC_V_STATUS	Transfer status field only, bit field offset
LCB_RST_DSC_V_XSTATUS	Transfer status field + direction, bit field offset
LCB_RST_DSC_V_DIR	Transfer direction, bit field offset 0 = out-bound, 1 = in-bound
LCB_RST_DSC_V_ADR	PCI address field, bit field offset

enum _LCB_RST_ERR_RCV

Enumeration of possible LCB RESULT receive errors in result items.

These are errors that the LCB detects when accepting data from a LATp fabric. That is these errors occur when the LCB reads response data.

The documentation only defines errors up to number 6, for a maximum of 7 errors. However the code index this with a 3-bit field. To be safe all 8 states must be covered

Code number 6 bears some special explanation. This happens when the LCB is asked to execute an illegal of inconsistent list. Examples of such lists are

• Request List with a 0 length
• Request Item with length not match the opcode
• Request Item that goes past the end of the request list

Since the inconsistency may be encountered at any point during the execution of the request list, the error cannot practically be reported in the result descriptor. (Perhaps it can, but the LCB has potentially already started writing the result list, so..) Anyway for whatever reason, this error is reported in the result item. Since the LCB does not in all cases know what the opcode of the request item is, the result item is always filled in with as OPCODE 0 result item with a length of 2 words and the error word set to 6.

The proper response by the software when encountering such an item is to immediately stop processing the result items.

Warning:

This makes processing statically defined request/result list a bit dicey. Suppose one defines a list with two items to access the CSR and FAULTS register, so that one knows apriori that the result list will consist of 2 result items corresponding to the responses to the register access requests. With errors of type 6, the software is likely required to make sure the opcode of the returned item is what is expected (i.e. it did not get transformed into an OPCODE 0, error = 6 response) and that the error is not 6.

Enumerator:

LCB_RST_ERR_RCV_SUCCESS	LATp success
LCB_RST_ERR_RCV_INVALID_HEADER_PARITY	LATp header parity error
LCB_RST_ERR_RCV_INVALID_DATA_PARITY	LATp data parity error
LCB_RST_ERR_RCV_UNDEFINED_3	LATp packet truncated error
LCB_RST_ERR_RCV_TRANSMIT_UNDERRUN	LATp result with transmit underrun error
LCB_RST_ERR_RCV_TIMEOUT	LATp result with timeout error
LCB_RST_ERR_RCV_INVALID_LIST	LATp invalid or internally inconsistent list encountered
LCB_RST_ERR_RCV_UNDEFINED_7	LATp undefined #7
LCB_RST_ERR_RCV_CNT	LATp maximum number of error

enum _LCB_RST_ERR_XFR

Enumeration of possible LCB RESULT in/out errors.

These errors occur when the LCB imports/exports data from the single board computer across the PCI bus and are reported as the low 4 bits of the result descriptor. Note that in/out is from the perspective of the LCB and includes both the 3 bit status field as well as the 1 bit direction flag.

Enumerator:

LCB_RST_ERR_XFR_OUT_SUCCESS	Outbound transaction okay
LCB_RST_ERR_XFR_OUT_PCI_MASTER_ABORT	PCI Master Abort
LCB_RST_ERR_XFR_OUT_PCI_PARITY_ERROR	PCI Parity Error
LCB_RST_ERR_XFR_OUT_PCI_TARGET_ABORT	PCI Target Abort
LCB_RST_ERR_XFR_OUT_UNDEFINED_4	Undefined error #4
LCB_RST_ERR_XFR_OUT_BUFFER_EMPTY	Buffer empty
LCB_RST_ERR_XFR_OUT_UNDEFINED_6	Undefined error #6
LCB_RST_ERR_XFR_OUT_Q_EMPTY	Result queue empty
LCB_RST_ERR_XFR_IN_SUCCESS	Inbound transaction okay
LCB_RST_ERR_XFR_IN_PCI_MASTER_ABORT	PCI Master Abort
LCB_RST_ERR_XFR_IN_PCI_PARITY_ERROR	PCI parity error
LCB_RST_ERR_XFR_IN_PCI_TARGET_ABORT	PCI Target Abort
LCB_RST_ERR_XFR_IN_UNDEFINED_4	PCI buffer full
LCB_RST_ERR_XFR_IN_UNDEFINED_5	Undefined error #5
LCB_RST_ERR_XFR_IN_UNDEFINED_6	Undefined error #6
LCB_RST_ERR_XFR_IN_UNDEFINED_7	Undefined error #7
LCB_RST_ERR_XFR_CNT	RESULT XFR error count

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