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LSEW_ctxTim.h File Reference

The time context, basically the binding of the Spectrum Astro time with the 1 PPS register. More...

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Data Structures

struct  _LSEW_ctxTim
 Holds information needed to fill in a time context. More...

Typedefs

typedef enum _LSE_CTXTIMFLAGS_S LSE_CTXTIMFLAGS_S
 Typedef for enum _LSE_CTXTIMFLAGS_S.
typedef enum _LSE_CTXTIMFLAGS_V LSE_CTXTIMFLAGS_V
 Typedef for enum _LSE_CTXTIMFLAGS_V.
typedef enum _LSE_CTXTIMFLAGS_M LSE_CTXTIMFLAGS_M
 Typedef for enum _LSE_CTXTIMFLAGS_M.
typedef _LSEW_ctxTim LSEW_ctxTim
 Typedef for struct _LSEW_ctxTim.

Enumerations

enum  _LSE_CTXTIMFLAGS_S {
  LSE_CTXTIMFLAGS_S_SIMULATED_VALUE = 1,
  LSE_CTXTIMFLAGS_S_SIMULATED_PPS_CPU = 1,
  LSE_CTXTIMFLAGS_S_SIMULATED_PPS_GEM = 1,
  LSE_CTXTIMFLAGS_S_NO_MESSAGE = 1,
  LSE_CTXTIMFLAGS_S_CNT_GPS_NO_LOCK = 12,
  LSE_CTXTIMFLAGS_S_IS_SOURCE_GPS = 1,
  LSE_CTXTIMFLAGS_S_SA_RSVD = 15
}
 Enumerates the timetone flags word, right-shift values. More...
enum  _LSE_CTXTIMFLAGS_V {
  LSE_CTXTIMFLAGS_V_SIMULATED_VALUE = 0,
  LSE_CTXTIMFLAGS_V_SIMULATED_PPS_CPU = 1,
  LSE_CTXTIMFLAGS_V_SIMULATED_PPS_GEM = 2,
  LSE_CTXTIMFLAGS_V_NO_MESSAGE = 3,
  LSE_CTXTIMFLAGS_V_CNT_GPS_NO_LOCK = 4,
  LSE_CTXTIMFLAGS_V_IS_SOURCE_GPS = 16,
  LSE_CTXTIMFLAGS_V_SA_RSVD = 17
}
 Enumerates the timetone flags word, right-shift values. More...
enum  _LSE_CTXTIMFLAGS_M {
  LSE_CTXTIMFLAGS_M_SIMULATED_VALUE = 0x1,
  LSE_CTXTIMFLAGS_M_SIMULATED_PPS_CPU = 0x2,
  LSE_CTXTIMFLAGS_M_SIMULATED_PPS_GEM = 0x4,
  LSE_CTXTIMFLAGS_M_NO_MESSAGE = 0x8,
  LSE_CTXTIMFLAGS_M_CNT_GPS_NO_LOCK = 0x0000FFF0,
  LSE_CTXTIMFLAGS_M_IS_SOURCE_GPS = 0x00010000,
  LSE_CTXTIMFLAGS_M_SA_RSVD = 0xfffe0000
}
 Enumerates the timetone flags word, in place mask values. More...

Detailed Description

The time context, basically the binding of the Spectrum Astro time with the 1 PPS register.

Author:
JJRussell - russell@slac.stanford.edu
   CVS $Id: LSEW_ctxTim.h,v 1.2 2007/04/08 20:12:20 russell Exp $

Typedef Documentation

LSE_CTXTIMFLAGS_M
 

Typedef for enum _LSE_CTXTIMFLAGS_M.

The flags word is a 32-bit word composed of 2 16-bit words. The most significant 16 bits belong to Spectrum Astro and are copied verbatim from the timetone message. As of this writing, only the least significant bit was defined as being set when the GPS lock was lost.
Warning:
Bit 30 has been usurped to indicate an internal inconsistency when decoding the data on the ground.
The least significant 16 bits are used by flight software. The low 4 bits are flags indicating problems with the timetone receiving mechanism. Essentially there are 3 signals to consider, the 1 PPS to the GEM, the 1 PPS to the receiving event processing CPU and the timetone message itself. Three of these bits indicate that one or more of the signals was not present at the required time.
The remaining 12 bits of the flight software 16 bit value is reserved for a count of the number of consecutive pulses that do have an imperfect timetone message or reception. This allows the user to determine how long the system has been flywheeling on Spectrum-Astro's internal oscillator or, more accurately, how long it has been since the last pristine message and reception. (For example, another error is the SIU missing its 1PPS message.)

LSE_CTXTIMFLAGS_S
 

Typedef for enum _LSE_CTXTIMFLAGS_S.

See LSE_CTXTIMFLAGS_M

LSE_CTXTIMFLAGS_V
 

Typedef for enum _LSE_CTXTIMFLAGS_V.

See LSE_CTXTIMFLAGS_M

Enumeration Type Documentation

enum _LSE_CTXTIMFLAGS_M
 

Enumerates the timetone flags word, in place mask values.

Enumerator:
LSE_CTXTIMFLAGS_M_SIMULATED_VALUE  The timetone value is simulated
LSE_CTXTIMFLAGS_M_SIMULATED_PPS_CPU  The receiving CPU did not receive a 1 PPS interrupted, so the 1 PPS was simulated by a timeout. In this case, the timetone message should be okay. This bit is really here for hardware accounting purposes. If this happens, it may indicate a faulty interrupt line to the CPU
LSE_CTXTIMFLAGS_M_SIMULATED_PPS_GEM  The GEM did not get the 1 PPS. This IS a serious problem. It means the CPU thought that at least 1 second has gone by, but the 7-bit index in the GEM's 1 PPS register did not advance. One should not trust the 1 PPS register.
LSE_CTXTIMFLAGS_M_NO_MESSAGE  The receiving CPU did not have a timetone message corresponding to the 1 PPS GEM register at the time the event arrived. This is a semi-normal situation, occuring when the event from the EBM (normally an event that occurs very near the 1-PPS time) arrives at the processing CPU before the timetone message arrives. When events are being processed on an EPU, this is just a race between the event from the EBM to the CPU and the timetone message from the SIU. Under normal conditions, a timetone message with this bit set will be followed (within a couple of events) by the real timetone message. However, the processing software, not wishing to wait an indeterminate amount of time for the real message, fabricates a timetone message, marking it with this bit
LSE_CTXTIMFLAGS_M_CNT_GPS_NO_LOCK  The count of consecutive timetone messages that have the GPS_NO_LOCK bit set.
LSE_CTXTIMFLAGS_M_IS_SOURCE_GPS  This is bit indicates the source of the time is the GPS. If not, the spacecraft lost the GPS lock and is simulating the timetone message by flywheeling off its own internal oscillator. This oscillator is very accurate, but one should exercise caution if the flywheel period lasts for a while.
LSE_CTXTIMFLAGS_M_SA_RSVD  Reserved for future use

enum _LSE_CTXTIMFLAGS_S
 

Enumerates the timetone flags word, right-shift values.

Enumerator:
LSE_CTXTIMFLAGS_S_SIMULATED_VALUE  The timetone value is simulated
LSE_CTXTIMFLAGS_S_SIMULATED_PPS_CPU  The receiving CPU did not receive a 1 PPS interrupted, so the 1 PPS was simulated by a timeout. In this case, the timetone message should be okay. This bit is really here for hardware accounting purposes. If this happens, it may indicate a faulty interrupt line to the CPU
LSE_CTXTIMFLAGS_S_SIMULATED_PPS_GEM  The GEM did not get the 1 PPS. This IS a serious problem. It means the CPU thought that at least 1 second has gone by, but the 7-bit index in the GEM's 1 PPS register did not advance. One should not trust the 1 PPS register.
LSE_CTXTIMFLAGS_S_NO_MESSAGE  The receiving CPU did not have a timetone message corresponding to the 1 PPS GEM register at the time the event arrived. This is a semi-normal situation, occuring when the event from the EBM (normally an event that occurs very near the 1-PPS time) arrives at the processing CPU before the timetone message arrives. When events are being processed on an EPU, this is just a race between the event from the EBM to the CPU and the timetone message from the SIU. Under normal conditions, a timetone message with this bit set will be followed (within a couple of events) by the real timetone message. However, the processing software, not wishing to wait an indeterminate amount of time for the real message, fabricates a timetone message, marking it with this bit
LSE_CTXTIMFLAGS_S_CNT_GPS_NO_LOCK  The count of consecutive timetone messages that have an imperfect timetone message or reception
LSE_CTXTIMFLAGS_S_IS_SOURCE_GPS  This is bit indicates the source of the time is the GPS. If not, the spacecraft lost the GPS lock and is simulating the timetone message by flywheeling off its own internal oscillator. This oscillator is very accurate, but one should exercise caution if the flywheel period lasts for a while.
LSE_CTXTIMFLAGS_S_SA_RSVD  Reserved for future use

enum _LSE_CTXTIMFLAGS_V
 

Enumerates the timetone flags word, right-shift values.

Enumerator:
LSE_CTXTIMFLAGS_V_SIMULATED_VALUE  The timetone value is simulated
LSE_CTXTIMFLAGS_V_SIMULATED_PPS_CPU  The receiving CPU did not receive a 1 PPS interrupted, so the 1 PPS was simulated by a timeout. In this case, the timetone message should be okay. This bit is really here for hardware accounting purposes. If this happens, it may indicate a faulty interrupt line to the CPU
LSE_CTXTIMFLAGS_V_SIMULATED_PPS_GEM  The GEM did not get the 1 PPS. This IS a serious problem. It means the CPU thought that at least 1 second has gone by, but the 7-bit index in the GEM's 1 PPS register did not advance. One should not trust the 1 PPS register.
LSE_CTXTIMFLAGS_V_NO_MESSAGE  The receiving CPU did not have a timetone message corresponding to the 1 PPS GEM register at the time the event arrived. This is a semi-normal situation, occuring when the event from the EBM (normally an event that occurs very near the 1-PPS time) arrives at the processing CPU before the timetone message arrives. When events are being processed on an EPU, this is just a race between the event from the EBM to the CPU and the timetone message from the SIU. Under normal conditions, a timetone message with this bit set will be followed (within a couple of events) by the real timetone message. However, the processing software, not wishing to wait an indeterminate amount of time for the real message, fabricates a timetone message, marking it with this bit
LSE_CTXTIMFLAGS_V_CNT_GPS_NO_LOCK  The count of consecutive timetone messages that have an imperfect timetone message or reception.
LSE_CTXTIMFLAGS_V_IS_SOURCE_GPS  This is bit indicates the source of the time is the GPS. If not, the spacecraft lost the GPS lock and is simulating the timetone message by flywheeling off its own internal oscillator. This oscillator is very accurate, but one should exercise caution if the flywheel period lasts for a while.
LSE_CTXTIMFLAGS_V_SA_RSVD  Reserved for future use

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