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36.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . 36-1

36.2 SPECIFICATION . . . . . . . . . . . . . . . . . 36-2

36.2.1 General . . . . . . . . . . . . . . . . . . . 36-2

36.2.2 Registers . . . . . . . . . . . . . . . . . . 36-2

36.2.3 Serial Link . . . . . . . . . . . . . . . . . 36-2

36.3 MESSAGE FORMATS . . . . . . . . . . . . . . . . 36-3

36.4 ERROR HANDLING . . . . . . . . . . . . . . . . . 36-3



36.7 CAMAC POWER DOWN AND RECOVERY . . . . . . . . . 36-4

36.8 SYSTEM TESTING PROVISIONS . . . . . . . . . . . 36-4

36.9 CAMAC COMMANDS . . . . . . . . . . . . . . . . . 36-5

36.10 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 36-9


36.1 GENERAL DESCRIPTION The PSi (Power Suppy Interface) is a single width CAMAC module designed to control and monitor a "large" magnet power supply. It is connected to the power supply subsystem via a two pair (4 wire) link carrying serial digital information in each direction. The power supply subsystem contains a "controller" which contains the DAC, the ADC, and the control/status registers, in addition to the analog and digital control systems for the power supply. The serial links talk to thos controller via a digital interface called the "PSi Remote Interface". This architecture is shown graphically in Figure 1. The PSi module contains a built-in ramping counter, serial error detection/generation circuits, and several self-test functions. It supports power supply ripple measurement, ground current measurement, and multiple transductor current readout, although these functions are not implemented in the present power supply controller being constructed for FFTB. Although it is functionally similar to the PSC I/II the PSi is significantly different in that all signals to/from the power supply are contained in a unified serial digital link. Although there are efforts to maintain some degree of code compatibility with PSC I/II there are significant differences due to the architectures of these systems. This chapter document primarily describes the overall system operation of the PSi module, with emphasis on the CAMAC interface so that operation software can be written. A separate document will describe the details of the PSi Remote Interface for design of that component. This information is not necessary for programming of the PSi.



36.2.1 General The PSi is a single witdh and runs on standard CAMAC voltages. The only power used is +6V and the current is estimated to be 1A. Serial connections will be on the front panel via a 4 pin LEMO connector. Other single pin LEMO connectors will provide TTL signals for counting uplink and downlink CRC errors, and TTL signals for the biphase encoded uplink and downlink messages for diagnostic purposes. In addition to the usual "X" LED indicating CAMAC activity there will be a pulsed LED to indicate serial CRC errors, and LEDs to indicate ramping in progress, Downlink Transmission Disabled, and Uplink Timeout.

36.2.2 Registers o DAC Fields: 18 to 24 bits, selectable, FFTB uses 18-bits o ADC FIelds: Up to 24 bits, FFTB uses 23-bits (bipolar) o Control Fields: Up to 16-bits, including 3-bits of ADC Mode o Status FIelds: Up to 16bits, including 3-bits of ADC Mode o Ramp Counter: 24 bits o Ramp Times: 16,32,64,128,256,512,1024 seconds nominal full scale ramp times, when the number of DAC bits is set properly (See Table 3) o DAC Direct Load: Available for ADC Self-test and after power-up only.

36.2.3 Serial Link o Configuration: Two twisted pairs, one (downlink) transmitting from the PSi module ot the power supply, the other (uplink) from the power supply to the PSi module o Bit Rate: 1.0 Mbits/second o Downlink Word Rate: Nominally 15 Khz continuous o Uplink Word Rate: Nominally 20 Hz continuous

POWER SUPPLY CONTROLLER (PSI) Page 36-3 o Word Length: 60-bits, both downlink and uplink, incl. sync. o Error Code: CRC-CCITT, 16-bits o Serial link elec: RS-485 Differential Drive and Receive o Termination: 100 ohms nominal at the receiving end o Line Length: 500 feet guaranteed (actual limit TBD) o Cable tye: Belden Datalene or equal o Modulation: Bi-phase, transition at each bit boundry, 1=transition in the center of the bit, 0=no transition at the center o Word Sync: Double length leading sync bit

36.3 MESSAGE FORMATS The message format for the downlink word is shown in Figure 2, and the message format for the uplink word is shown in Figure 3. The coding of the ADC mode bits is described in Table 4. The loopback bit (bit 1 of downlink message) is used by the PSi Remote Interface to connect the downlink to the uplink return path for system testing purposes described in Section 8. Note that the two power supply control signals, DC ON and Reset Interlocks are pulsed (0.5 sec.). One-shots in the PSi module cause these signals to be "1" on the link for fixed time periods.

36.4 ERROR HANDLING The use of CRC codes in the serial links provides a very high degree of error detection capability for both radon and burst errors. In both the PSi module and the PSi Remote interface the respective register load operations should be inhibited when an error is detected in a received message. In otherwords the entire assembled message should be discarded when an error is detected. In the PSi Remote Interface an error flag should be set which is then sent back as bit 42 in the next uplink message. Sending back the uplink message automatically resets the error flag in the Remote Interface. This error bit when received in the PSi module sets a "downlink" error flag. Likewise a CRC error detected in an uplink message to the PSi sets an "uplink" error flag. This error flag is also set when an incomplete (shortened) uplink messgage is received by the PSi. These error flags can be read by a single CAMAC operation which also resets the two flags.

POWER SUPPLY CONTROLLER (PSI) Page 36-4 It is expected that occurance of errors in these links will be rare. Frequent or continual errors represent excessive noise or possible hardware problems requiring attention.






36.9 CAMAC COMMANDS o F0 A0: Read DAC set point, (R1-R24) o F0 A1: Read ADC, offset binary, (R1-R24); if Q=0, ADC is not ready or UPLINK timed out has occurred Table 6 bit 24 - Sign ( 0=neg, 1=positive ) bit 23 - Overload (inverse of sign bit) bits 1-22 data + Full Scale +10.0V B00000 (hex) Zero 0.0V 800000 (hex) - Full Scale -10.0V 400000 (hex) Overload BFFFFF (hex) Note 1: The ADC is a bipolar Analog Device 1175K. The output format is in offset binary with 23 data bits, including 22 bits of resolution and a sign bit. The overload bit provided on the unit is not available in the CAMAC readout. However, an overload will show up as all one's in the 23 data bits that are read out. The unit has a full scale of +/- 5V but with a 2:1 divider the effective range is +/- 10V. The unit can read properly up to 25% over full scale. Normaly the ADC reads positive but it can read negative when the power supply polarity is reversed. In ADC self-test mode the gain factor between the DAC and the ADC is unity, since the DAC full scale is +10V. Negative readings will not occur in this case. o F0 A2: Read Power Supply Control Register Table 1 R/W Bit Input/Output -------- ------------ 1 DC ON (Pulsed 0.5 sec) Reset Interlocks (Pulsed 0.5 sec) 3 Remote Enable (1=Enable, 0=Disable) 4 Select Normal Polarity (1=Normal, 0=Reverse) 5-13 Future Note: 1. Reset Interlocks must be set ahead of a ps turn on sequence. This is because the Remote Enable and Remote enable readback status bits are latched. 2. The default state for the Normal Polarity control status bit is "0" indicating reverse polarity for those devices that have a polarity switch. Therefore, for devices with a polarity switch the Normal Polarity (from the ps control reg readback)

POWER SUPPLY CONTROLLER (PSI) Page 36-6 Normal Polarity status (from the ps status reg) must both be set to "0" for Reverse Polarity. or both be set to "1" for Normal Polarity. For a device without a polarity switch only the Normal polarity status bit is used to determine the device state, "1" for Normal and "0" for Reverse polarity. o F0 A3: Read Power Supply Status, (R1-R16) Table 2 Read Bit -------- 1 Power Supply Interlock (1=OK) 2 Magnet Interlock (1=OK) 3 System Ready (1=Ready) 4 DC on (1=ON) 5 Normal Polarity (1=Normal, 0=Reverse) 6 Remote/Local Control (1=Remote, 0=Local) 7 Ground Current Interlock (1=OK) 8 PPS Status (1=OK) 9 Remote Enable Readback (1=Enable) latched 10 ADC data Valid (1=Valid, 0=Timeout) 11 Spare 12 Spare 13 Spare 14 Uplink Message Valid (1=Valid, 0=Timeout) 15 Spare 16 Spare Note: 1. The ADC timeout is set to 66 msec. The status data is the reflection of the Q status received from the F0A1 CAMAC operation. 2. The UPLINK timeout is set to 120 msec. If the uplink is invalid the status data=0. 3. If the device is set in normal polarity the Normal Polarity status bit will be "1". The default state is to set this bit to "1". o F1 A0: Read ramping rate, (R1-R3). o F1 A1: Read ADC input mode from remote interface, (R1-R3) o F1 A2: Read the number of DAC bits, stored on PSi, (R1-R3) o F2 A0: Read and Reset CRC error flag, (R1-R2) R1=DOWNLINK, R2=UPLINK o F3 A0: Read Serial Number, (R1-R16) o F3 A1: Read Module Id, (R1-R16)
POWER SUPPLY CONTROLLER (PSI) Page 36-7 o F3 A2: Read Module Revision, (R1-R16) o F16 A0: Set DAC and start ramping, (W1=W24) Ramp time and number of bits must be set first. Permitted only when Downlink Transmission ENABLED Q=0 if not permitted o F16 A1: Write set point register directly, (W1-W24) Permitted only when Downlink Transmission DISABLED; Q=0 if not permitted o F16 A2: Write Power Supply Control. (See Table 1) o F17 A0: Set ramping rate, (W1-W3) Table 3 W3 W2 W1 Full Scale Ramping Time (Sec) __ __ __ _____________________________ 0 0 0 1073.77 (Note 2) 0 0 1 536.88 0 1 0 268.44 0 1 1 134.22 1 0 0 67.11 1 0 1 33.55 1 1 0 16.77 1 1 1 0.0 (Note 1) Note 1: Zero ramp time is to be used in ADC Self-Test ONLY. Zero ramp time permitted only if PS is OFF (eg Remote Enable must be logic "0" in the PS control register). Note 2: Ramp time of 1073.77 seconds is set by Initialize or by CAMAC Power ON. Note 3: Correct full scale ramp times are achieved ONLY when the number of DAC bits is set equal to the actual number of bits in the remote interface DAC (ie: locate in the ps chassis). o F17 A1: Select ADC input mode Table 4 W3 W2 W1 Input -- __ __ _____________ 0 0 0 Analog1 input 0 0 1 Ripple Current (Future) 0 1 0 DAC Out Monitor (Future) 0 1 1 ADC Self-Test 1 0 0 Analog In 2 (Future) 1 0 1 Ground Current Mon (Future) 1 1 0 Future 1 1 1 Future Notes: 1. At present 6/93, the controller supports Analog In 1 and ADC Self-Test. 2. When reading ADC Mode, the status comes back from the ps controller via the Remote Interface
POWER SUPPLY CONTROLLER (PSI) Page 36-8 which confirms that the selected mode is supported and is active. 3. After changing the ADC Mode the software MUST wait at least 100 ms before reading the ADC register or the ADC mode Register. 4. The ADC Mode is set to Analog In 1 after Initialize or CAMAC Power ON. o F17 A2: Write the number of DAC bits, set in PSi (W1-W3) Table 5 W3 W2 W1 Input -- __ __ _____________ 0 0 0 18 (Default) 0 0 1 19 0 1 0 20 0 1 1 21 1 0 0 22 1 0 1 23 1 1 0 24 1 1 1 Not Used. Note: Selecting the number of bits in the DAC assures that the programmed ful scale ramp times will be achieved for that number of DAC bits. For greater thatn 18 bits the resolution during ramping may be reduced. The number of DAC bits is set to 18 by Initialize or by CAMAC Power ON. o F19 A0: Set Module Serial Number, (R1-R16); Requires that jumper be installed on module; Wait 10 ms before any other F19 or F3 operation; o F19 A1: Set Module Id, (R1-R16); Requires that jumper be installed on module; Wait 10 ms before any other F19 or F3 operation; o F19 A2: Set Module Revision, (R1-R16); Requires that jumper be installed on module; Wait 10 ms before any other F19 or F3 operation; o F24 A1: Disable DOWNLINK transmission (Prior to Power Down) o F24 A2: Disable PSi Module Self-Test (Return to Normal Op) o F24 A3: Disable Cable Loopback Test (Return to Normal Op) o F26 A1: Enable DOWNLINK transmission (After Registers Restored) o o F26 A2: Enable Psi Module Self-Test (Internal Loopback); Downlink transmission must be enabled and; Cable Loopback should be enabled.
POWER SUPPLY CONTROLLER (PSI) Page 36-9 o F26 A3: Enable Cable Loopback Test; Disconnect Remote Interface; Downlink transmission must be enabled. F27 A0: Test ramping status; Q=0 indicates ramping in progress o F27 A1: Test DOWNLINK transmission; Q=1 indicates Enabled o F27 A2: Test PSi Module Self-Test, Q=1 indicates Enabled o F27 A3: Test Cable Loopback Test, Q=1 indicates Enabled o Z*S2: Set all internal registers to zero except ADC register o X: X=1 on all commands. o Q: Q=1 on all valid commands, except where indicated. o Z: Initialize PSi module; Set all registers and status F-F; to "0". Set Downlink Transmission to Disable. Set all; tests to Disabled. Power Supply Status Register and; ADC Data Register will be 0 until the first update; arrives. After issuing a "Z" wait 50 msec before; reading thest registers.; o Power on: Same as Z.


36.11 RESPONSIBLE ENGINEERS Andrew H. Gioumousis

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Contact (until Aug. 15, 1996): Jeffrey Miller
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