Linac RF Frequency Synchronization


The purpose of the system is to synchronize the linac frequency at the time of booster injection, the only time that the linac has any RF in it. This is done by shifting the phase of the linac frequency so that it always has the same phase with respect to the booster frequency when the chopper fires, the only time that the beam goes through the linac.

Currently the linac is almost exactly, but not quite, 8 times the frequency of the booster (2856MHz/8 = 357Mhz). The booster frequency is used as the basis of the 2856MHz, but a little phase is added to it each cycle so that it slows down enough to generate the 2856MHz during the few microseconds in which the klystron is powered. This gives a synchronous 2856MHz that starts when the peaking strip fires and ends when the system counter expires. After that, the frequency is 8*358.5MHz, which doesn't matter since there is no power in the klystron during that time.

The frequency synchronization is implemented using a LLRF phase and amplitude controller (PAC) designed for LCLS. Documentation:

The input signals into the PAC: The output signals from the PAC (not including monitor points): The PAC also has 2 ethernet ports and 1 console port used by the control system.

PAC Detail Description (from LCLS)

The control board uses a MAX5875 two channel 16 bit, 200MSPS, DAC to clock out waveforms which are stored in a Xilinx Spartan 3 FPGA. The coldfire processor is memory mapped to two 2k 16bit sample waveforms in the FPGA. On a trigger, the two waveforms are simultaneously clocked out the dual DAC. Voltage waveforms of up to 1.25Volts are sent out to the IQ modulator. The FPGA has an internal trigger mode to continuously write out a waveform. The unit is calibrated by writing a cosine to one waveform and a sine to the other. In this mode the unit becomes a single side band modulator.

There are 8 analog input to PAC board which use the 14 bit, 8 single ended channels, MAX1149 ADC. The ADC is connected through the serial port to the FPGA. The FPGA places the data from the ADC in eight 16 bit registers which are memory mapped to the Arcturus uCDIMM. Three of the eight input channels are used to measure temperature of the control board, the RF Module, and the SSSB, if applicable. The two 12VDC power supplies in the SSSB are monitored along with the bulk 5 Volt supply for the control board and the 15V bulk supply for the RF Module. The last ADC channel is used to monitor SSSB power level.


An EPICS application runs on the b140-ioclinpac IOC. Substitution and database files for linac RF sync records (see database list) reside under $EPICS_APP/PAC. The SPEAR EPICS PV Database web page is used to add records to history ( B140-IOCLINPAC and LIN-RF).

Operator Interface


Contact: Stephanie Allison and Jim Sebek
Last Modified: Feb 12, 2009