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8.2i IP Update #2 - Release Notes and Known Issues for CORE Generator ISE 8.2i IP Update 2 (8.2i_IP2)

Answer Record: 23831
Family: Software
Product Line: Coregen
Part: Coregen
Version:
Last Modified: 09/28/06 15:28:47
Status: Active
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Problem Description:

Keywords: networking, Ethernet, MAC, XAUI, gigabit, SPI, SPI4, SPI42, SPI-4.2, SPI4.2, PL4, GFP, Tri-Mode, generic, framing, procedure, SONET, system, packet, interface, fibre, channel, DVB-ASI, FIFO, fifo16, cam, asynchronous, 8b10b, decoder, ip4_g, embedded, Aurora, wrapper, PCI, PCI-X, PCI32, PCI64, PCIX, PIPE, PCI Express, UCF Generator, counter, DSP, Binary Counter, Comparator, Complex Multiplier, Distributed Arithmetic FIR Filter, DVB S2 FEC Encoder, Floating-point Cores, MAC, MACC, Pipelined Divider, RAM-based Shift Register, TCC Encoder 3GPP, LogiCORE, CORE, COREGen, CORE Generator , VLYNQ , CAN

This Answer Record contains Release Notes for ISE 8.2i IP Update 2 (also known as 8.2i_IP2) and includes the following:

- IP Related Known Issues
- CORE Generator Known Issues
- Platform Support
- Installation Instructions
- MXE Simulation Library


Solution 1:

Release Notes and Known Issue for IP included in this IP Update release:

- (Xilinx Answer 23897) RocketIO Wizard v1.2

- (Xilinx Answer 23849) LogiCORE Block Memory Generator v2.2
- (Xilinx Answer 23848) LogiCORE Distributed Memory Generator v3.2
- (Xilinx Answer 23847) LogiCORE FIFO Generator v3.2

- (Xilinx Answer 22321) LogiCORE PCI v3.60, PCI-X v5.60, PCI v4.1, PCI-X v6.1 and PCI/PCI-X UCF Generator v1.0
- (Xilinx Answer 22320) LogiCORE PCI Express v3.3
- (Xilinx Answer 22322) LogiCORE PCI Express PIPE v1.5

- (Xilinx Answer 23919) LogiCORE Gigabit Ethernet MAC v8.1
- (Xilinx Answer 23921) LogiCORE Tri-mode Ethernet MAC v3.2
- (Xilinx Answer 23920) LogiCORE 10 Gigabit Ethernet MAC v8.1
- (Xilinx Answer 23922) LogiCORE Virtex-4 Tri-Mode Ethernet MAC Wrappers v4.3

- (Xilinx Answer 23846) LogiCORE SPI-4.2 v8.2

- (Xilinx Answer 23876) LogiCORE CAN v1.4

- (Xilinx Answer 23509) LogiCORE VLYNQ v1.2

- (Xilinx Answer 23902) Release Notes and Known Issues for all DSP products:

--DDS Compiler (Direct Digital Synthesis) v1.0
--FIR Compiler v2.0
--Floating point Operators v3.0
--Reed Solomon Decoder v6.0
--Interleaver/Deinterleaver v5.0
--TCC Decoder 3GPP v3.0
--TCC Encoder 3GPP v3.0
--TCC Encoder 802.16e v2.0
--Viterbi v6.0


General CORE Generator Known Issues

(Xilinx Answer 20478) 8.2i CORE Generator - A COREGen project created on PC does not behave properly on Linux and Solaris systems
(Xilinx Answer 20919) 8.2i CORE Generator - IP "readme.txt" file contains generic information for ".v" and ".vhd" files, which is not applicable for Reference Designs
(Xilinx Answer 21364) 8.2i CORE Generator - Attempting to open a core customization GUI opens the data sheet for the selected IP core
(Xilinx Answer 21955) 8.2i CORE Generator - An error occurred while running Java. This may be due to memory limitations
(Xilinx Answer 22548) 8.1i CORE Generator/ISE Simulator - "WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst <instance name> of Component <core name>"
(Xilinx Answer 22549) 8.1i ISE/CORE Generator - When running Manage Cores through Project Navigator on Linux 32, IP cores cannot be customized when Java memory is set to 2048 or above
(Xilinx Answer 22581) 8.2i CORE Generator - Option to open previous project will open SysGen created project
(Xilinx Answer 22583) 8.2i CORE Generator - Dual Port Block Memory v6.3 - "Show Coefficients" does not display the content of the COE file if the depth is greater than 511
(Xilinx Answer 22600) 8.2i CORE Generator - Selecting View Version information for a specified IP Core results in "ERROR:sim:165 - Could not find version info"
(Xilinx Answer 22601) 8.2i CORE Generator - Fragmented or seemingly incomplete error messages are being displayed in the COREGen console window
(Xilinx Answer 22605) 8.2i CORE Generator - Project -> Project Options... "Preferred Implementation Files" label is not fully visible on Solaris and Linux platforms
(Xilinx Answer 22906) 8.2i CORE Generator - "ERROR:encore:59 - The name cannot begin with a digit"
(Xilinx Answer 23395) 8.2i CORE Generator - Some IP cores provided in CORE Generator have incomplete or inaccurate simulation models


Platform Support

- Windows 2000 Professional (Service Pack 2 to 4)
- Windows XP Home (Service Pack 1)/Professional (Service Pack 1)
- Sun Solaris 8/9
- Linux Red Hat Enterprise 3.0 (32-bit and 64-bit)


Installation

You might need system administrator privileges to install the update.

First ensure that 8.2i SP2 or later is installed. Xilinx ISE design tools updates are available from the Download Center at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

Install the IP Update by following one of the two methods listed below:

Method 1: Automated Update using the Web Installer

1. Start the CORE Generator Web Installer (from the CORE Generator main GUI, select Tools -> Software Update...). This starts up the WebUpdate application. If you are prompted for a proxy host, contact your administrator to determine the proxy host address and port number that you should be using to get through your firewall.

2. Select "ISE 8.2i IP Update 2" from the list of updates in the Available Packages panel.
If you are prompted to enter a login name and password, use the Xilinx login and password that you normally use to download IP Updates and Service Packs.

3. Click "Ok" to initiate a download of the update. After the update is downloaded, the WebUpdate Installer displays a dialog box indicating that it is terminating the CORE Generator session and installing the downloaded archive. Another dialog box will indicate when the update installation is complete; when this appears you can then restart CORE Generator.

4. To confirm that you have installed the update properly, select Help -> About.

Method 2: Manual Installation

Use this method if you are behind a firewall and do not know your proxy settings:

1. Close the CORE Generator application, if it is running.

2. Download the appropriate ".zip" file from the following location and save it to a temporary directory:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp by specifying:

"ISE IP Update" as the Download Type
"8.2i" as the "ISE Version"
Your desired operating system for the "Operating System" selection (the same .zip file is supplied for all platforms)

3. Extract the ".zip" file (ise_82i_ip_update2.zip) archive to a temporary location.

4. In the root level of the unarchived directory structure, run the setup(.exe) executable or setup.pl script to install the update.

5. Restart CORE Generator. CORE Generator automatically detects and displays the newly installed IP cores.

6. Determine whether the installation was successful by verifying that the new cores are visible in the CORE Generator GUI.


MXE Simulation Library

The cores delivered with this IP Update require updated XilinxCoreLib libraries. For information on how to obtain the latest pre-compiled MXE libraries, see (Xilinx Answer 10616).

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