Designer v8.1 Release Notes
(Nov 19, 2007)
Thank you for your interest in Actel's Designer v8.1 FPGA Physical
Implementation Software.
Designer Block Flow
- The Designer Block flow is enhanced such that you can now
instantiate multiple blocks into your design project. You can instantiate the
same block multiple times in the same design, or you can instantiate several
different Designer blocks in the same design. Designer blocks can be viewed
and managed within the MultiView Navigator tools.
SmartGen
- A Flash*Freeze management macro has been added to support IGLOO/e devices.
This macro manages a clean entry and exit from Flash*Freeze state ensuring the
design saves state. It also hand shakes with user logic to delay actual entry
into the Flash*Freeze mode if desired. It filters user clocks before and after
actual the Flash*Freeze state to ensure that user logic always receives clean
clock signals. Clock domains requiring state-saving during Flash*Freeze should
have the clock routed through this macro.
SmartPower
- Power Profiles. SmartPower allows you to create a power
"profile" for a design. A power profile is a combination of active, standby,
Flash*Freeze, or user created operational modes. You specify the amount of
time (as a percent of total) the design will be in each operational mode.
SmartPower calculates the total power for each mode, plus total power based on
the weighted average of the power consumption of all modes. Consequently, a
more realistic report of power is provided. Power profiles can be created to
test different configurations in order to create an optimal design.
- Battery Life Estimator. By entering the current capacity
of a specific battery, SmartPower provides the battery life based on "always
active" operation, as well as for power profile scenarios. Using a power
profile provides a more realistic estimation of battery life, since most
battery operated applications are seldom in a full active mode all of the
time.
- Clock Domain power analysis calculates and displays the
power consumption for all Clock Domains in the design. This helps you
visualize and potentially address specific clock domains that are responsible
for excessive power consumption. Power consumption for the domain's Clock Tree
and Data Path are shown in a visual dialog, including the percent contribution
of the total for each.
- Peak Power Analysis. Designer v8.1 provides a cycle-based
(or cycle-accurate) power analysis. Based on a VCD simulation file, SmartPower
will report one power value per clock period (or half-period) for a given
waveform instead of a typical average power for the whole simulation. This
feature allows you to easily evaluate every cycle in terms of power
performance to determine the peak power. This feature is also helpful to
understand and further minimize power consumption by facilitating the analysis
of data-dependent power variations, as well as dynamic power variations due to
clock-gating or clock frequency variations.
- Spurious Transition Analysis. SmartPower 8.1 identifies
functional as well as undesirable spurious "hazard" transitions that occur
during switching that all contribute to higher dynamic power consumption.
Typically during a clock cycle a gate with multiple inputs experiences
multiple hazard transitions before settling to the correct logic level.
SmartPower 8.1 analyzes the transitions that occur during each clock cycle and
a report displays all hazards and respective power consumption associated with
each net. A comprehensive user interface dialog allows the user to specify the
nets and number of cycles to be reported.
- Data Change Report. This new report lists specific data
and other changes that have occurred in the software over time. A reference
number and topic summary are shown. Contact Tech Support for more information
on the subject.
SmartTime
- Constraint Wizard. A new wizard for creating timing
constraints guides you to easily set up the specific constraints for your
design. Page-by-page dialogs with graphical aids assist you to understand and
set constraints for overall/explicit clocks, I/O requirements or specific
clock delays with minimum/maximum input and output delays, generated clocks,
and input and output pin clock requirements. A summary dialog allows you to
confirm all selections made.
- Constraint Scenarios. You can now set up, save, and test
timing constraint "scenarios" to help you better understand the timing
capability and performance of your design. When going into a constraints
scenario dialog, you can create a set of constraints that can be used to
analyze your design pre-layout, and/or to drive timing driven place-and-route.
Multiple constraint scenario dialogs can be open simultaneously to allow you
to easily view the constraint sets that are to being tested. Both Layout and
SmartTime Options allow for selection of saved scenarios, plus you can import
an SDC file into a specific scenario, or export a selected scenario with an
SDC file.
- Constraint Coverage Report. SmartTime provides
statistical data on the actual constraint tests that are performed. The report
shows the number of constraints that are met, not met, or are untested.
Supported checks are: setup, hold, recovery, removal, and output. Adjustments
can then be made in SmartTime to ensure that more constraints are tested and
met.
- New TCL commands. 44 new TCL commands have been added.
See on line help or the User Guide for the complete listing.
- Data Change Report. This new report lists specific data
and other changes that have occurred in the software over time. A reference
number and topic summary are shown. Contact Tech Support for more information
on the subject.
MultiView Navigator
- Routing View for Axcelerator devices. The MultiView
Navigator now shows the "Route" view of the design in addition to the
"Ratsnest" view. The "Route" view is only available after place-and-route is
complete. In this view, you can see a representation of the routing segments
used in the design. You can use the Display Settings dialog box from the View
menu to change the default color schemes that are used to display the routing
segments.
- Reserve Pins. This feature allows you to reserve a
package pin that will not be used in the current design, and it is expected
that the design will be used in a revision of the design in the future. An
example is when you begin a design with a larger device that you intend to
implement later in a smaller device. Because there may be pins on the smaller
device that are not bonded, you want to be sure that the pin assignments
created on the larger device are compatible with the pins on the smaller
device. This feature reserves the pins on the larger device that are not
bonded on the smaller device. Pins in the current device that are not bonded
in the target device will be marked as "reserved". You can explicitly reserve
a pin in the PinEditor, I/O Attribute Editor, or by importing a PDC constraint
file with the "reserve" PDC command.
Designer Layout Options
- Power Driven Layout. A "Power Driven Layout" Option
drives placement of the design based on an imported simulation Value Change
Dump (VCD) file, or SmartPower’s design analysis data. With little to no
impact on timing of the design, the PDL flow dynamically guides placement of
the physical layout of IGLOO/e, Fusion, and ProASIC3/E designs to achieve the
lowest possible power consumption for low power and portable applications. If
timing of the design is of concern, Actel recommends running Timing Driven
Place-and-Route first and check the timing results. If the timing is met, then
re-run layout using power driven layout, and re-check timing. If low power
consumption is the main concern, run Timing Driven Place-and-Route and Power
Driven Layout simultaneously. There is small run-time cost when using power
driven layout.
- Multi-pass Layout. The Multi-Pass Layout configuration
has been significantly enhanced to correct ambiguities of the previous version
and add new features. Enhancements are:
- Specify a starting seed index
- Select Minimum Delay timing violations to compare layout results
- Select Total Negative Slack as a measurement criterion in addition to
Worst Slack, or the frequency of the slowest clock, or a specified clock
- Stop or not stop on first pass without violations
- File name conventions are changed to avoid/eliminate confusion
- <adbFileName>_timing_r<runNum>_s<seedIndex>.rpt
- <adbFileName>_timing_violations_max_r<runNum>_
s<seedIndex>.rpt
- <adbFileName>_timing_violations_min_r<runNum>_
s<seedIndex>.rpt
- <adbFileName>_iteration_summary.rpt
- <adbFileName>_r<runNum>_s<seedIndex>.adb
- Improved summary report provides detailed and clear results
New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
| A3PE3000 |
FG484 |
STD, -1, -2 |
COM, IND |
| -F |
COM |
New Packages
The following new IGLOO packages are available.
| Device |
Package |
Speed Grade |
Temperature Range |
| AGL030v2 |
µCS81 (4x4) |
STD, -1 |
COM, IND |
| AGL030v5 |
µCS81 (4x4) |
STD, -1 |
COM, IND |
| AGL600v2 |
CS281 |
STD |
COM, IND |
| M1AGL600v2 |
CS281 |
STD |
COM, IND |
| AGL600v5 |
CS281 |
STD |
COM, IND |
| M1AGL600v5 |
CS281 |
STD |
COM, IND |
Package Updates
The following devices have package updates as noted.
| Device |
Package |
Re-compile required? |
| AFS600 |
PQ208, FG256, FG484 |
Yes |
| M1AFS600 |
| M7AFS600 |
Device Updates
A3P030, AGL030V2, AGL030V5 .adb invalidation. All existing
.adb files for these devices will be invalidated and put back to pre-compile
state. Designs must be re-compiled and re-run through place-and-route using
v8.1. Any constraints should be saved and imported into the project.
A3PE3000 .adb invalidation. All existing .adb files for the
A3PE3000 will be invalidated and put back to pre-compile state. Designs must be
re-compiled and re-run through place-and-route using v8.1. Any constraints
should be saved and imported into the project.
New Programming File Generation Support
Updated PDB/STAPL file generation. Previously generated programming files for
the following devices must be regenerated using this v8.1. FlashPro v6.1 is
required for device programming.
- AFS250, AFS600/M1AFS600/M7AFS600, AFS1500
- AGL600/M1AGL600
Programming File Generation is enabled for the following devices:
- AGL030
- M1AGL600
- A3P030
- M1A3P600
- M1A3PE600
- M1A3PE1500
ProASIC3/E to IGLOO/e Design Migration
A migration wizard is available to assist you in converting an existing A3P/E
design to a compatible device/package IGLOO/e design. After layout has been run
and an adb has been created in Designer for your A3P/E design, go to Tools
> Setup, and select IGLOO (or IGLOOe) as the migration family.
You must first confirm that the desired IGLOO/e device and package is supported
in the Designer software. If the IGLOO/e device/family is not yet available in
the software, you will get a message saying that there is no compatible
die/package available.
Support on Windows 2000 and Linux RedHat 3.0 ends with Designer v8.1.
Disk ID license versions of Designer run on Windows Vista. Full Windows Vista
support is planned for Q2 2008.
For more information, view the complete System
Requirements.
Designer v8.1 requires a current Designer v8.0 license. Register for a free Designer
Evaluation or Gold license, or contact your local Actel Sales office to
purchase a Designer Platinum license.
Unless otherwise noted, these issues apply to all
devices.
Designer
72166 - Incorrect output drive strength for the IGLOO
AGL030. The 2X output drive strength selection only provides 1X drive
strength on LVTTL I/Os due to a software issue that causes incorrect
configuration of the I/O. This will be resolved in the next Libero IDE/Designer
service pack.
Designer Programming File Generation
72168 – Libero IDE/Designer v8.1 SVF programming file is not correct
for the IGLOO/e and ProASIC3/E devices. Programming these devices using
an SVF file generated by Libero IDE/Designer v8.1 will cause programming to
fail.
Workaround: Use either STAPL or PDB
programming file generation. This issue will be resolved in the next available
Service Pack.
SmartGen
67614 – Failed to load the STAPL
file which contains FlashROM with the same region names (A3P/E)
SmartTime
54900 – Designer quits when
executing the st_restore script command
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