Designer v8.2 Release Notes
(Jan 31, 2008)
Thank you for your interest in Actel's Designer v8.2 FPGA Physical
Implementation Software.
ProASIC3L
Designer v8.2 introduces support for Actel's new low-power ProASIC3L devices
that feature 40 percent lower dynamic power and 90 percent lower static power
than its previous-generation ProASIC3 FPGAs. The
new flash-based family combines dramatically reduced power consumption with up
to 350 MHz operation.
The following devices and packages are available:
| Device |
Package |
Speed Grade |
Temperature Range |
| A3P250L |
VQ100, PQ208, FG144, FG256 |
STD, -1 |
COM, IND |
| A3P600L |
PQ208, FG144, FG256, FG484 |
STD, -1 |
COM, IND |
| A3P1000L |
PQ208, FG144, FG256, FG484 |
STD, -1 |
COM, IND |
| A3PE3000L |
PQ208, FG324, FG484, FG896 |
STD, -1 |
COM, IND |
Power-Driven Layout
Power-Driven Layout is available for the ProASIC3L devices. This Layout
Options feature typically reduces the dynamic power consumption of a design
by 10%.
ProASIC3L Programming Support
Programming File Generation is enabled for the A3P600L devices. Programming
is available using FlashPro v6.2.
IGLOO
New Devices
| Device |
Package |
Speed Grade |
Temperature Range |
AGL250V2
AGL250V5 |
CS196 |
STD, -1 |
COM, IND |
AGLE3000V2
AGLE3000V5 |
FG484 |
STD, -1 |
COM, IND |
Characterized Timing Data
SmartTime timing data for the IGLOO family is now based on actual silicon
characterization. Characterized timing data may have a minor performance affect
on current designs.
Enhanced Min-delay
SmartTime now provides support for conservative minimum delay/hold-time
analysis based on IGLOO characterized silicon timing data. This new feature
eliminates the need to over guard-band a design for minimum delay, providing a
more comprehensive, precise way to perform chip-to-chip evaluation of external
setup/hold and clock-to-out timing.
ProASIC3
New Package Support
| Device |
Package |
Speed Grade |
Temperature Range |
| A3PE3000 |
FG484, FG896 |
STD, -1 |
COM, IND |
Programming Support
Programming File Generation is enabled for the M1A3P250 devices. Programming
is available using FlashPro v6.2.
Characterized Power Data
SmartPower power data for the ProASIC3 family is now based on actual silicon
characterization. Characterized power data may have a minor affect on current
designs.
Fusion
Programming Support
Programming File Generation is enabled for the AFS1500 and M1AFS1500 devices.
Programming is available using FlashPro v6.2.
Characterized Timing Data
SmartTime timing data for Fusion devices is now based on actual silicon
characterization. Characterized timing data may have a minor performance affect
on current designs.
Enhanced Min-delay
SmartTime now provides support for conservative minimum delay/hold-time
analysis based on Fusion characterized silicon timing data. This new feature
eliminates the need to over guard-band a design for minimum delay, providing a
more comprehensive, precise way to perform chip-to-chip evaluation of external
setup/hold and clock-to-out timing.
FlashPro v6.2
FlashPro v6.2 supports programming for the following:
- ProASIC3L: A3P600L
- ProASIC3: M1A3P250
Disk ID license versions of Designer run on Windows Vista. Full Windows Vista
support is planned for Q2 2008.
For more information, view the complete System
Requirements.
Designer v8.2 requires a current Designer v8.0 license. Register for a free Designer
Evaluation or Gold license, or contact your local Actel Sales office to
purchase a Designer Platinum license.
Unless otherwise noted, these issues apply to all
devices.
ProASIC3 to ProASIC3L or IGLOO migration
72815 – Device migration may not be allowed because maximum VCO
Frequency is different for ProASIC3/E, IGLOO/e and ProASIC3L
Using
the ProASIC3/E to ProASIC3L or IGLOO/e migration there is a check that makes
sure the VCO maximum frequency is within the valid range for the target
device.
The following message will be displayed:
Error: CMP435: Illegal
configuration for PLL 'dpll_0/Core'.
Regenerate your PLL using the latest
version of SmartGen.
The message is incorrect, and should be displayed as:
CMP449: The VCO frequency for the
PLL/DYNCCC <instance name> does not fall within the allowed range for
the device in use. The allowed range is minvco MHz to maxvco MHz.
Before you can continue migration, you must make sure that you modify the
frequency of the ProASIC3/E design so the maximum VCO frequency falls within the
valid range of the ProASIC3L or IGLOO/e devices. For more information, please
refer to the ProASIC3L or the IGLOO/e data sheets.
IGLOO and ProASIC3L Flash*Freeze Flow
73424 – DRC fails after running synthesis when the ULSICC macro is
used
If the ULSICC macro is instantiated, and if 'run DRC after
synthesis' is on in the Configure Design Flow dialog, running the
Design Rule Check (DRC) will fail with an error:
Error: Designer failed to
generate files. View the Designer log
file:"\designer\impl1\designer_genhdl.log" for more details. Failed
When you click on the link to open designer_genhdl.log you can see an
error:
Error: CMP859: An instance of
Low-Static
ICC
'.../FlashFreezeCtrl_wrapper_inst/U0/FlashFreeze_FSM_inst/ULS
\ICC_INSTANCE'
was found in the design. This macro is allowed only in Flash*Freeze Mode
Type-2. Please specify a Flash*Freeze port in the Compile options to enable
the Type-2 mode. Refer to the ProASIC3L data sheet for details on Flash*Freeze
modes.
This error is generated because the Flash*Freeze port name was not specified
in the design. You can discard this error since there is no way to enter this
port name before running DRC.
Required user action: Disable 'Run DRC after
synthesis' in the Configure Design Flow dialog if a ULSICC is
instantiated in your design.
72767 – Precision v2007a.8 synthesis does not include support for
Flash*Freeze
The current version of Precision synthesis does not
support the IGLOO/e or ProASIC3L Flash*Freeze feature.
Workaround: Use the current version of Synplify
Pro/Synplify AE 9.0.A2 supplied with Libero IDE v8.2.
Designer
73415A – IBIS aborts when exporting A3PE3000L files
IBIS
file export will display an error when attempting to export file for A3PE3000L
for COM temperature range.
73415B – IBIS model IND temperature range is not available for
currently supported ProASIC3L devices
Industrial temp range IBIS
model data is not available for A3P250L, A3P600L, A3P1000L, or
A3PE3000L.
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