Block Flow allows you to create a
design that can be defined as a unique block for immediate instantiation into a
design and/or be preserved and set aside for future use. A completed block is
optimized using the customary synthesis, simulation and place-and-route flows,
and may or may not include I/Os. Placement of components within the block and
timing are preserved. When creating a new project in Libero or Designer, select
a "Block Design Flow" instead of a standard flow, after which the block can be
published to a repository. The block can then be instantiated into a design
using the conventional Libero design flow. Libero IDE v7.3 Block Design supports
Fusion, IGLOO/e, ProASIC3/E, Axcelerator, and RTAX-S family devices.
SmartGen Enhancements for Fusion Analog
System Builder (ASB)
- Fusion NGMUX macro enhancement: A second clock input of
the NGMUX is now allowed to drive the NGMUX input as well as other core logic.
This enhancement supports the Fusion Analog System use model of continuously
driving the ACM CLK with a slow clock ( < 10 MHZ ) and simultaneously
driving the rest of the logic with a switching fast/slow clock, without using
an additional global resource.
- PreScaler On/Off Selection. The Voltage Monitor, Current
Monitor, and Differential Voltage Monitor configuration dialogs have been
updated to provide a option to select between using or bypassing the
prescaler. When the prescaler is selected, a tooltip shows what prescaler
value is being used for the configuration.
SmartTime
- Bottleneck Analysis: A bottleneck is a point in the
design that contributes to multiple failing paths. This new 7.3 feature finds
and lists all bottlenecks according to severity and occurrences. The list has
a format similar to the existing "datasheet" report.
- Clock Analysis for Virtual Clocks: In some cases, paths
from one FPGA may sensitize or be sensitized by paths outside the FPGA (e.g.
on the board, or on another FPGA.) The new Virtual Clock capability in
SmartTime 7.3 enables you to specify a constraint for a clock that is running
outside the FPGA, and thus do timing analysis on the design as it interacts
with this "virtual" circuitry.
SmartTime Timing
Changes
- A3P/E timing is updated, now based on the silicon
characterization. This update includes all A3P/E devices except the A3PE600.
The impact on timing for existing designs is minimal.
- Enhanced Min Delay (EMD) support for ProASIC3/E -
SmartTime now provides support for precise minimum delay/hold-time analysis
based on A3P/E characterized silicon timing data. This new feature eliminates
the need to over guard-band a design for minimum delay, providing a more
comprehensive, precise way to perform chip-to-chip evaluation of external
setup/hold and clock-to-out timing.
- UFROM Clock-to-Out timing has been extended for A3P250
and A3P1000 devices. If your A3P250 or A3P1000 design includes a UFROM, re-run
SmartTime to obtain the correct timing information.
- FIFO Write Enable (WEN) and Read Enable (REN) setup time
is increased by a depth dependent delay to better align with the silicon
capability. (A3P250 and AFS600 Rev A/B)
- IBIS model for the APA1000 FG896 is updated to include
support for MIL temperature.
SmartPower
- Initialization with SmartTime Timing Constraints – links
SmartPower to SmartTime. For each clock in SmartPower, the equivalent clock
and its constraints are found in SmartTime. The power is then calculated using
the user's actual timing constraints. This approach gives a more accurate view
of the power consumption based on actual expected operating frequencies, and
enables the user to keep frequency information between SmartTime and
SmartPower in synch.
- Advanced Power Analysis for Fusion – Now includes
analysis for all Fusion-specific low-power modes
- adds Analog Block, Embedded Flash Memory, RC and Crystal (XTL)
Oscillators to "Type"
- adds VCC3.3A analog to "Rail"
- analyzes power contribution for the A/D converter Quad blocks
- Advanced Power Analysis for Memories – This feature adds
the capability to view power consumption for memory blocks such as RAM, FIFO
and embedded flash memory based on specifics of the memories, such as number
of active bits, aspect ratio of the memory blocks, the number of memory
blocks, etc.
- An Instance Properties Pop-Up box can be accessed with a
right click on any instance in the Analysis Tab. The pop-up box provides
detailed information about the selected instance.
- Improved Thermal Analysis and Static Power Calculation:
Static Power calculation is now based on Junction Temperature. Two modes are
available:
- Mode 1: Tjunction is stable as a function of Operating Condition only.
The Operating Condition can be changed in the preferences window.
- Mode 2: The user changes Tambient and the Thermal-resistance is used to
compute T-junction. If the estimated T-junction exceeds the Maximum of the
range, a warning is issued
New Devices and
Packages
| Family |
New Devices |
New Packages |
Package Updates |
| ProASIC3/E |
A3P030 QFN132
A3P030 VQ100 |
A3PE1500 FG484
A3PE1500 FG676 |
A3PE1500 PQ208 * |
| IGLOO |
AGL030 VQ100
AGL030 QN132 |
- |
- |
| Fusion |
M7AFS1500 FG256 |
- |
AFS1500 FG256 |
* Current designs will be invalidated and must be
re-compiled and re-run through P&R.
RTAX-S Program File Generation Dialog modified to
provide Original Programming Algorithm (OPA) or UMC Modified Algorithm (UMA)
options (61264)
The Program File
Generation User Interface for RTAX-S is enhanced to accommodate a new
programming algorithm (AFM) to be used for UMC production devices. The "Fuse
Export Options" UI Dialog Box now provides selections for either OPA or UMA AFM
generation. The specific device selections are:
- RTAX4000S: UMA support only
- RTAX250S, RTAX1000S, RTAX2000S: UMA and OPA support
- Default selection is for OPA AFM generation
New Macros
Pipelined FIFO has been added for
Axcelerator devices. The details are included in the
Macro Guide.
Online Help
61973 - Online Help on Linux and Solaris Operating
Systems does not include 7.3 updates. Online Help contains
Libero/Designer v7.2 SP1 Content. For Libero/Designer v7.3 help, please refer to
the PDF files included with your v7.3 installation. Go to the Help menu and
select "Reference Manuals".
Block Design Flow
59174/60119 - Generics and Parameters
are not supported in Block instantiation in the Top level Design (All
Devices)
60369 - Do not instantiate a Block component more
than once.
The Block flow in 7.3 is limited to one instantiation of
the block. Libero does not issue a warning if more than one block is
instantiated into the design, however Designer will fail when the netlist is
compiled. Instantiating multiple blocks in the block flow is a future
enhancement.
Designer
60732 - Export SDF TCL command
failure (All Devices)
61444 - Spine support is disabled
on A3P030 and AGL030 devices
62374 - Syntax error in STAPL player when using
encrypted files (A3P/E, AFS)
An encrypted A3P/E, AFS, M7 STAPL file
is not compatible with Actel's STAPL player. A syntax error will occur when the
file is executed through the player. FlashPro and Sculptor software are not
affected.
Designer Compile
61348 - Designer compile error
message does not reflect AGL030 RAM support correctly
62092 - A3P030 or AGL030 designs in the VQ100
package do not support all 6 CLKBUFs. A design that contains 6 CLKBUFs
using this die and package will issue a compile error. Only 5 CLKBUFs can be
instantiated at this time.
SmartGen
61893 - SmartGen does not differentiate core
selections for A3P030/AGL030. A3P030 and AGL030 devices do not contain
PLLs, RAMs, or FIFOs. (see specifications for these devices at http://www.actel.com/products/igloo/
and http://www.actel.com/products/pa3/).
When designing with these devices, SmartGen includes PLLs, RAMs, and FIFOs in
the available cores list, and the devices can be selected and configured for the
design, but the design will fail later in the flow. Do not select these cores
when using these devices.
MultiView Navigator (MVN)
62087 - Incorrect count of I/O region resources for
A3P/E and IGLOO/e. The IO resource count (region properties) is
counting the unbounded IO as an available IO resource.
Workaround: There is no impact on user really since
the Design Rule Check (DRC) will not allow you to do any assignments to the
unbonded I/Os. This issue is only a resource display issue.
62086 - Properties dialog box shows incorrect ADLIB
name for the User Low Static ICC (ULSICC) core. (IGLOO/e) When you
right click and Select Properties on an instantiated ULSICC macro, the name of
the cell in the properties dialog in the MultiView Navigator (MVN) appears as
"ADLIB:UUSERB". It should appear as "ADLIB:ULSICC".
Workaround: The tooltip in the MVN shows the
correct cell name.
62462 - Show Routes option is not functional in
v7.3 (ProASIC/ProASICPLUS)
The "Show Routes"
option in the MVN, which has been functional in previous versions, is not
functional in v7.3. The RatsNest display however is functional. This issue will
be fixed in an upcoming release
SmartTime
62341 - External setup/hold displayed in the Summary
have a wrong value (All Families)
The worst external recovery value
for a clock domain is set instead of the worst external setup value in the
summary (in the GUI and the timing report) when the clock domain has an external
recovery and removal/recovery checks are enabled.
Workaround: The correct external setup values are
displayed in the list of paths.
Disabling removal/recovery checks will fix
the values in the summary.
62342 - The datasheet does not show the external
setup information for generated clock domains (All Families)
The
SmartTime datasheet does not show the external setup information for the
registers which have the generated clock as their clock source. The SmartTime
datasheet should show external setup information with respect to the external
clock.
62344 - LVDS clocks are not shown under the Explicit
Clock (A3P/E)
Differential input signals have two inputs, which are
joined by a buffer. This causes the potential clock to be ignored. In the
SmartTime Add Clock interface, you can add the output of the differential buffer
using the GUI, but it will not provide timing data for that path. Only adding
the individual differential pins will provide timing data for the path.
62345 - SmartTime shows false violation for a path
that does not exist (APA)
For nets and cells removed by Designer
compile, SmartTime uses a 0 delay. In some cases, this can lead to false min
delay violations.
Workaround: Check the differences between the
optimized and the original netlist in netlist viewer to check if it is a false
path.
62346 - The Bottleneck Report "cost_type -
path_count" option is not working in Tcl (All Families)
A Tcl script
"cost_type - path_count" does not work correctly. The report will generate
correctly using "cost_type - path_cost". The option works correctly in the
SmartTime Graphical User Interface.
62347 - Minimum Pulse Width is 0 for IO cells in
A3P030. This will only affect the maximum frequency for clock domains
without register-to-register paths or with short register-to-register
paths.
