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61.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . 61-1
61.2 VETO MODULE DESCRIPTION . . . . . . . . . . . . 61-2
61.3 MASTER MODE . . . . . . . . . . . . . . . . . . 61-2
61.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . 61-3
61.5 DIAGNOSTIC FEATURES . . . . . . . . . . . . . . 61-3
61.5.1 Diagnostic Information - All status register
61.5.2 Diagnostic Control - The first 8 bits of status
61.6 TIMING DESCRIPTION . . . . . . . . . . . . . . . 61-5
61.6.1 Data Format (fig. 3) . . . . . . . . . . . . . 61-5
61.6.2 System Delay Times . . . . . . . . . . . . . . 61-5
61.6.3 Total Delay . . . . . . . . . . . . . . . . . 61-6
61.6.4 System Timing (fig. 4) . . . . . . . . . . . . 61-6
61.6.5 Delay from Beam time to data valid . . . . . . 61-6
61.7 MODULE FUNCTION CODES . . . . . . . . . . . . . 61-6
61.8 MODULE WIDTH . . . . . . . . . . . . . . . . . . 61-7
61.9 SIGNAL LEVELS . . . . . . . . . . . . . . . . . 61-7
61.9.1 Write Sync J1 & Read Sync J2 . . . . . . . . . 61-7
61.9.2 Trigger Input J3 . . . . . . . . . . . . . . . 61-7
61.9.3 Serial Port J4 . . . . . . . . . . . . . . . . 61-7
61.9.4 Number of Fault Input Channels J5 . . . . . . 61-7
61.9.5 Input Levels J5 . . . . . . . . . . . . . . . 61-7
61.9.6 Select Output J5 . . . . . . . . . . . . . . . 61-8
61.9.7 Power Required . . . . . . . . . . . . . . . . 61-8
61.9.8 Protection . . . . . . . . . . . . . . . . . . 61-8
61.9.9 Operating Temperature Range . . . . . . . . . 61-8
61.10 FRONT PANEL . . . . . . . . . . . . . . . . . . 61-9
61.10.1 Front Panel Indicators . . . . . . . . . . . . 61-9
61.10.2 Front Panel Connectors (J1 Through J5) . . . . 61-9
61.10.3 Pin assignments as follows: . . . . . . . . . 61-9
61.11 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 61-10
61.12 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 61-10 CHAPTER 61 VETO MODULE (VETO)
61.1 GENERAL DESCRIPTION The Fast Veto System provides a way for micros gathering BPM or other beam related data to be told about "bad" beam pulses. The system uses about seventy (70) CAMAC modules distributed throughout the SLC to gather fault information and send it, in coded form, to any micros which may require it. These CAMAC modules are referred to as Veto modules. The Veto modules are connected together by a 2 pair cable. One, the write pair, is used to signal faults and the other, the read pair, is used to receive them. E.I.A. Standard RS-422 serial transmission is used on both pairs. The serial bit stream contains 32 bits of data which is received and modified if necessary and then passed along to the next module. The delay though each module is approximately one and a half bit times (approx. 3 microseconds) for both the read and the write busses. A 32 bit data stream containing all zeros, starts at MCC and is passed from module to module, ending up at the Injector.(see fig. 1) Any module may modify this data if a fault condition exists at its location. The output of the Veto module at the injector contains the summary of all modules in the SLC. At this point the write pair is connected to the read pair and the data is sent back to MCC, allowing all modules to read this veto pattern. This pattern is stored in a register so that it can be read by the local micro if required. It is expected that the veto bus pattern will have a single bit associated with each area i.e. Damping Rings, Positron Source, Linac etc. The SLC can probably be divided into 7 such areas; therefore, the 32 bit pattern should provide sufficient expansion capacity. The actual cabling is done using the Multiple Access Communication Highway. This is a multi-pair cable which is shared with other systems. Access to this cable is through a MACH 1 Interface. There is typically one MACH 1 Interface per VETO module. The MACH 1 provides automatic bypassing when the VETO module is unpowered or disconnected. Veto modules in each sector may receive fault inputs concerning the condition of klystrons, kickers or Machine Protection Devices. There are two types of faults which may be signaled by a device, "fast" faults, which only affect a single beam pulse, or "slow" faults,
VETO MODULE (VETO) Page 61-2 faults which may affect all beam pulses for one or more seconds. A device signals a fast fault by asserting a fault condition, on one input of a Veto module, for a single 1/360th period. A device signals a slow fault by asserting a continuous level on an input of the Veto module. The Veto module responds to either of these fault conditions by sending a programmed pattern on the write pair.
61.2 VETO MODULE DESCRIPTION The VETO module is a single width CAMAC module. It has 5 connectors on the front panel. One 36 pin AMP connector is used for inputting faults from devices. A 15 pin "D" connector is used to communicate with the serial bus. Two LEMO connectors are provided for diagnostics. A third LEMO connector is provided as a trigger input for the "Master" Veto module in MCC. A block diagram of the Veto module is shown in figure 2. The fault inputs of the module are optically isolated. A 3 to 30 volt input represents a logic true, while the lack of an input represents a fault. The inputs are enabled or masked by the Fault Mask register. If a fault condition exists on any of the enabled inputs the contents of the Write Pattern register is "OR"ed with the pattern on the write pair. Transmissions occur approximately 1.35 Msec after nominal beam time and at a 360HZ rate. The transmission time is determined by a single "Master" module in MCC. After the Write Pattern has been processed by all modules it is then presented to the read bus. The 32 bit data pattern on the serial read bus is stored in the Data Pattern register. This register then contains the data regarding the previous data from the previous beam pulse. The timing is such that the data in this register will be valid if read as part of the normal micro timing job i.e. when the local broadcast patterns are sent. A CAMAC read of this register will find Q=1 if valid data has been received. Reading this register resets Q (Q=0). The veto module also contains the Output Select Pattern register. This register is used to operate the Select Output, which appears on the 36pin AMP connector. This output has an optically isolated transistor which is normally conducting and which ceases conduction when one of the bits of the Output Select Pattern register matches an equivalent data bit on the serial read bus.
61.3 MASTER MODE A single module in MCC operates as the master for the system. This mode is specified by asserting a bit (W8) in the status register. Normally the master module should have a zero write field specified (W5 - Status Reg.) and zero data in the Write Pattern register. The master module can place data on the write bus by asserting a fault (W1) and loading the data into the Write Pattern Register.
VETO MODULE (VETO) Page 61-3
61.4 REGISTER DESCRIPTION o DATA PATTERN REGISTER (32 bits) - This register contains the veto pattern as read from the veto bus. This data is will be valid (Q=1) if the module is receiving patterns at the correct time and without a parity error. o WRITE PATTERN REGISTER (32 bits) - This register contains the veto pattern which is sent if a fault occurs. o OUTPUT SELECT REGISTER (32 BITS) - This register selects the bit or combination of bits that will cause an output to be generated (as previously described). This output may be filtered by requiring that an output condition exists for two consecutive serial data cycles, thus making it only sensitive to long faults. o FAULT MASK (16bits) - This register is used to gate signal appearing on J-1. This can be used to disable unused inputs or to ignore malfunctioning devices. o STATUS REGISTER (16bits) - This register is used to control and monitor special functions of this module. STATUS REGISTER FORMAT Bit Description _______________________________________ R1,W1 Assert fault continuously R2,W2 Bypass Write Logic R3,W3 Bypass Read Logic R4,W4 Enable WRITE pattern R5,W5 Generate Zero Data on Write input R6,W6 Generate Zero Data on Read input R7,W7 Enable double pulse Filter R8,W8 Enable Master mode R9 Write data not received R10 Write data received with error R11 Read data not received R12 Read data received with error R13 Time-out occurred i.e. rate < 360 HZ R14 Input Fault occurred R15 Status of Select Output R16
61.5 DIAGNOSTIC FEATURES The status register provives several important pieces of diagnostic information and control.
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61.5.1 Diagnostic Information - All status register bits are latched and are reset after a CAMAC read. The reset insures that all information is current. A list of diagnostic information contained in the status register follows: o Write data not received (R9) - This bit indicates that write data has not been received since the last read of this register. o Write data received with error (R10) - This bit indicates that write data has been received and a parity error occurred. o Read data not received (R11) - Same as write o Read data received with error (R12) - Same as write o Time-out occurred (R13) - This indicates that the internal time timed out. Normally read or write data is recieved at a 360HZ rate. A logical true condition usualy indicates some type of transmission problem or a trigger problem in the master module. o Input Fault occurred (R14) - This bit indicates that one or more of the enabled fault inputs has faulted. o Status of Select Output (R15) - This indicates one or more of the logically true bits of the Output Select Register were also true on the read data bus.
61.5.2 Diagnostic Control - The first 8 bits of status register are control bits. The state of these bits is readable through CAMAC. A list of the status register diagnostic control bits follows: o Assert fault continuously (R1,W1) - This bit generates a continous fault condition. If Write Pattern is enabled (W4) this write pattern will be "or"ed with the data on the write bus and should be seen by all modules. o Bypass Write Logic (R2,W2) - This is an electrical bypass of the write logic. The write logic regenerates the received data before passing it on to the next module. This control is therefore useful in diagnosing problems with this write logic. o Bypass Read Logic (R3,W3) - Same as with write logic. o Enable Write Pattern (R4,W4) - This bit allows write data to be generated by this module when a fault condition exists.
VETO MODULE (VETO) Page 61-5 o Generate Zero Data on Write (R5,W5) - A logical true on this bit forces the input data on the write bus to appear to be zero, regardless of what came into the module. This would aid in finding a "bad" module i.e.,one that is corrupting the data on the write bus. o Generate Zero Data on Read (R6,W6) - Same as with write logic. o Enable double pulse Filter (R7,W7) - This bit effects the Select Output by requiring that the condition causing an output be present ffor two consecutive cycles. (see description of Output Select Register) o Enable Master mode (R8,W8) - This bit enables Master Mode (as previously described.
61.6 TIMING DESCRIPTION
61.6.1 Data Format (fig. 3) The data is Bi-phase modulated where a one is signaled by a transition in the middle of the data frame pulse and a zero by the lack of a transition. This modulation method is used in the SLC serial CAMAC system. A string of continuous zeros is sent between data transmissions. There is a 4 bit preamble preceding the data to provide a start of message sync and parity bit at the end for data integrity. This 4 bit preamble is unique to the veto system and allows for the expansion of the cable system for some other use. The continuous zero stream between messages helps to stabilize the line and reduce distortion. The data rate would be 500Kbaud, during transmissions.
61.6.2 System Delay Times o There are 32 bits of data plus parity and a 4 bit preamble for a total of 37 bits. The total message time is (37 x 2) or 74 Microseconds. o There is a delay of 1 1/2 Bits per module (3 Microseconds), on both the read and the write data paths, and a total of 70 modules in the system. Thus the total propagation delay is (3x2x70) 420 Microseconds. o The total cable length is approximately 50,000 feet. Thus the total cable delay will be 65-75 Microseconds.
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61.6.3 Total Delay The total system delay is as follows: Message Time 74 Module Propagation Delay 420 Cable Delay 75 ------- Total System Delay 549 Microseconds
61.6.4 System Timing (fig. 4) o The delay from Beam time to Veto fault input (PIOP delay) is approx. 1.3 Milliseconds. o The input delay in the Veto module is approx. 50 Microseconds. o The Veto system delay is approx. 0.55 Milliseconds.
61.6.5 Delay from Beam time to data valid PIOP Delay 1.30 Module Input Delay .05 Veto System Delay .55 ------- Delay from Beam time 1.90 Milliseconds
61.7 MODULE FUNCTION CODES The CAMAC functions accepted by the VETO Module are as follows: Function Description Q Code Response ----------------------------------------------- F0*A(0,1) Read READ DATA PATTERN Q=DATA VALID F0*A(2) Read FAULT INPUTS Q=1 F0*A3 Read STATUS REGISTER Q=1 (same as F1*A5) F1*A(0,1) Read WRITE PATTERN Q=1 F1*A(2,3) Read OUTPUT SELECT REGISTER Q=1 F1*A4 Read FAULT MASK Q=1 F1*A5 Read STATUS REGISTER Q=1 (same as F0*A3) F17*A(0,1) Write WRITE PATTERN Q=1 F17*A(2,3) Write OUTPUT SELECT REGISTER Q=1 F17*A4 Write FAULT MASK Q=1 F17*A5 Write STATUS REGISTER Q=1
VETO MODULE (VETO) Page 61-7 F25*A7 Generate Fault (one cycle only) Z*S2 Power On Reset (Clears status register)
61.8 MODULE WIDTH Single.
61.9 SIGNAL LEVELS
61.9.1 Write Sync J1 & Read Sync J2 o TTL logic one pulse. Approximate duration, 75 Microseconds. Source impedance 430 ohms
61.9.2 Trigger Input J3 o NIM level one (-16 milliamps +/- 4ma. into 50 ohms)
61.9.3 Serial Port J4 o Serial inputs and outputs are E.I.A. RS-422 Compatible. o
61.9.4 Number of Fault Input Channels J5 16, (numbered 0 through 15).
61.9.5 Input Levels J5 o "0" = -30 through +1 volts,
VETO MODULE (VETO) Page 61-8 o "1" = +3 through +30 volts. o (Undefined from +1 volt to +3 volts.) o Optically isolated with current drawn not to exceed 10 milliAmps for a 30 volt input.
61.9.6 Select Output J5 o Optically isolated darlington transistor. o Maximum output current - 100 milliamperes o maximum on-state voltage - 1volt @ 50 ma. o maximum off-state voltage - 60 volts
61.9.7 Power Required o +6 volts, 1.8 Amps maximum o +24 volts, 1.0 Amps maximum (depends upon external loading)
61.9.8 Protection o Inputs will withstand +/- 30 volts indefinitely, and +/- 60 volts for one (1) second without damage. o The +6 and +24 volt lines are each fuse +6volts - 3 amp fuse +24volts - 1 amp fuse
61.9.9 Operating Temperature Range 10 to 6O degrees Celsius.
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61.10 FRONT PANEL
61.10.1 Front Panel Indicators "X", red LED, "OK", green LED, "OK" lighted indicates that the Select Output is not activated
61.10.2 Front Panel Connectors (J1 Through J5) J1,J2,J3__3 each, 1 pin Female LEMO Receptacle J4 __ 1 each, 15 pin "D" Female Receptacle ITT CANNON # DA15SA J5 __ 1 each, 36 pin AMP P/N 204731-1.
61.10.3 Pin assignments as follows: WRITE SYNC J1 Produces a positive TTL sync pulse every time serial write data is received. The Source READ SYNC J2 impedance is 430 ohms. This output may be terminated into a 50 ohm load. TRIGGER IN J3 This NIM level input is used to trigger a zero field write when the module is in master mode. SERIAL PORT J4 TERM SIGNAL RETURN COMMENTS WRITE IN -1 -9 Serial write data output RELAY + -2 Relay for write bus (see note) RELAY - -10 " " " " WRITE OUT -3 -11 Serial write data input GROUND -4 READ OUT -5 -12 Serial read input from serial bus RELAY + -6 Relay for Read bus (see note) RELAY - -14 " " " " READ IN -7 -15 Serial read outputs to serial bus GROUND -8 " -12 NOTE: 24volts - actuates port in MACH 1 Interface FAULT INPUTS J5 INPUT SIGNAL RETURN || OTHER SIGNALS # || CONNECTION / FUNCTION || 00 -A1 -A2 || 01 -A3 -A4 || -C9 FAULT OUTPUT (pos.) 02 -A5 -A6 || 03 -A7 -A8 || -C10 FAULT RETURN (neg.) 04 -A9 -A10 ||
VETO MODULE (VETO) Page 61-10 05 -A11 -A12 || -C11 +24 VOLTS FUSED @ 1A 06 -B1 -B2 || 07 -B3 -B4 || -C12 Ground 08 -B5 -B6 || 09 -B7 -B8 || 10 -B9 -B10 || 11 -B11 -B12 || 12 -C1 -C2 || 13 -C3 -C4 || 14 -C5 -C6 || 15 -C7 -C8 ||
61.11 DRAWING PACKAGE NUMBER 233-252
61.12 RESPONSIBLE ENGINEER Mike Browne