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6.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . 6-1
6.2 CAMAC COMMAND DESCRIPTION . . . . . . . . . . . . 6-2
6.3 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . 6-4
6.3.1 Power Supply Requirements . . . . . . . . . . . 6-4
6.3.2 Temperature . . . . . . . . . . . . . . . . . . 6-4
6.3.3 Connector and Interface Specifications . . . . . 6-4
6.4 FRONT PANEL DESCRIPTION . . . . . . . . . . . . . 6-6
6.4.1 Connectors . . . . . . . . . . . . . . . . . . . 6-6
6.4.2 Status LED's . . . . . . . . . . . . . . . . . . 6-7
6.5 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . . 6-7
6.6 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . . 6-7 CHAPTER 6 CABLE ACCESS TRANSMITTER (CAT)
6.1 GENERAL DESCRIPTION The Cable Access Transmitter (CAT) is a triple width CAMAC module which accepts 16-bit wide data words either from CAMAC or from a front panel connector. Using the Synchronous Data Link Control (SDLC) protocol, the CAT transmits them as packets at a maximum 2 Mbaud rate. The SDLC output bit stream is made available as a baseband TTL level signal on the front panel, but typically this is looped back into the module to an RF Modulator whose output is also available on the front panel. The RF Modulator, manufactured by Phasecomp, is described in the 'MODEMS' chapter as the 'Pattern Modem Data Transmitter'. Together, the CAT and CAR provide a high speed data communications link over the SLCNET cable not requiring processor intervention. Data that is to be transmitted by the CAT is buffered by a 64 word deep FIFO. When the data appears at the output of the FIFO and a Clear To Send (CTS) signal has been asserted (by the modem, for example), a finite state machine implemented with an FPLS (Field Programmable Logic Sequencer) and a Multi-Protocol Communications Controller (MPCC) (Signetics SCN2652) transmit the data as an SDLC message. SDLC protocol specifies that a secondary station address (SSA) field (which in this case specifies the destination of the message) and a control field be sent before the data field. The CAT therefore allows transmission of either the contents of an SSA register or the broadcast address (0FFH) in the address field, and allows two bits of information to be encoded in the control field. One of the control field bits is used to generate a LAM in the CAR, while the other bit is reserved for the implementation of multiword messages. When loaded by CAMAC, the SSA/broadcast option and LAM bits are encoded in the address field. When the CAT is loaded through the front panel connector, the LAM bit is loaded as a 'seventeenth' data bit, while the content of the SSA field is determined by a jumper within the module. Data is transmitted with the least significant byte first, in least to most significant bit order. Generation and transmission of the CRC checksum, opening and closing flags, and zero bit insertion as specified by the SDLC protocol are automatically handled by the MPCC chip. As a result, there is an overhead of at least 48 bits associated with the transfer of each (16 bit) message.
CABLE ACCESS TRANSMITTER (CAT) Page 6-2 The transmit clock rate and baseband encoding scheme is determined by a daughter board which plugs into a 14 pin DIP socket on the CAT. Peculiarities of the Phasecomp modems require that a return-to-one baseband encoding scheme be employed, and this is accomplished by the board detailed in the SLAC 123-639-02 drawing package. Upon application of power or initialization of the module as a response to a CAMAC command (Z*S2, F9, or F11), the MPCC is ready to transmit data (all MPCC registers set to 00H), the SSA register is reset to 00H, inputs from the front panel are enabled, and the modem control Request To Send (RTS) is not asserted, turning off the modem's transmitter. For ease in on-line diagnosis and troubleshooting, all registers within the CAT that may be written to are able to be read from by CAMAC, provided that the internal data bus is not being used for the transmission of a message.
6.2 CAMAC COMMAND DESCRIPTION FIFO WRITE F16 A0 W16-W1 are written into the FIFO. SSA = Broadcast, No LAM interrupt F16 A1 W16-W1 are written into the FIFO. SSA = Broadcast, LAM interrupt F16 A2 W16-W1 are written into the FIFO. SSA = SSA REGISTER, No LAM interrupt F16 A3 W16-W1 are written into the FIFO. SSA = SSA REGISTER, LAM interrupt F16 A5-A8 Reserved for future implementation of multiword packets. (X=Q=0) SSA WRITE F16 A4 W8-W1 are written into the SSA REGISTER FIFO READ F0 A0-A3 R18 = DADR2 R17 = DADR1 R16-R1 = DATF-DAT0 SSA READ F0 A4 R8-R1 = SSA REGISTER CHNL STATUS F1 A0 R8 = FIFO OUTPUT READY R7 = FIFO INPUT READY R6 = CTS (MODEM CLEAR TO SEND) R5 = FRONT PANEL ENABLEd R4-R1 are set by jumpers to correspond to the modem transmit frequency MPCC STATUS F1 A1 R8-R4 undefined R3 = MPCC Transmit Underrun R2 = MPCC Transmit Active R1 = MPCC Transmit Enable
CABLE ACCESS TRANSMITTER (CAT) Page 6-3 WRITE F17 A8-A15 W8-W1 are written into the MPCC's MPCC REG'S control registers 0-7. These are all set to zero whenever the module is init- ialized, and for normal operation need not be altered. It may be useful to change the contents of some of these registers when troubleshooting defective modules or modifying the their function. In this case the Signetics SCN2652 data sheets should be consulted for further details. READ F1 A8-A15 *** NOTICE *** MINIMUM CAMAC CYCLE TIMES AND MAXIMUM SPECIFIED CHIP DELAYS AS A RESULT OF SCN2652 MODIFICATIONS MAKE IT IMPOSSIBLE TO GUARANTEE THE VALIDITY OF THIS DATA. DEVICE FUNCTIONALITY CAN ALWAYS BE VERIFIED WITH A SLOWER CRATE CONTROLLER. THESE COMMANDS SHOULD NOT BE USED FOR ROUTINE DIAGNOSTICS. *** NOTICE *** R8-R1 are read from MPCC control registers 0-7. In general, these will all be equal to zero. For more informa- tion, consult the Signetics SCN2652 data sheets. MPCC REG'S XMTR ENABLE F26 A0 Sets RTS (REQUEST TO SEND), which turns on the transmitter. XMTR DISABLE F24 A0 Resets RTS, which turns the transmitter off FPNL ENABLE F26 A1 Enables inputs from the front panel FPNL DISABLE F24 A1 Disables inputs from the front panel RESET F9 Reinitializes the CAT by clearing the F11 FIFO, setting all MPCC registers to 0, Z*S2 setting the SSA register to 0, enabling front panel inputs, and resetting RTS. An X response is generated for each of the above commands A Q response is generated if the command was able to be executed. Possible reasons for not getting a Q response are FIFO input or output not ready on FIFO writes or reads, or the request was made in the middle of an SDLC transmission and the internal data bus was not free.
CABLE ACCESS TRANSMITTER (CAT) Page 6-4
6.3 ELECTRICAL SPECIFICATIONS
6.3.1 Power Supply Requirements o The CAT circuit board requires +6 Volts @ 1.25 A. o The Phasecomp modem requires +24 Volts @ 0.5 A.
6.3.2 Temperature The CAT will operate as specified between 0 and 65 degree Celsius.
6.3.3 Connector and Interface Specifications
188.8.131.52 J1 - Front Panel Parallel Data Connector - o The J1 connector mates to the standard SLC 36 conductor cable. o 16 Data bits are received as RS-422 (differential TTL) signals. Each Data pair is terminated with a 100 ohm resistor. o The LAM bit is received as an active high RS-423 (TTL) signal. It is terminated by 100 ohms to ground. o The Front Panel Data Ready (FPDR) signal is received as an active low RS-423 signal. It is terminated by a 200 ohm pull-up to +5 and a 200 ohm pull-down to ground. The 16 differential Data inputs and the LAM bit must be stable for a minimum of 0 nsec before FPDR is asserted. In order for data to be correctly written into the CAT, FPDR must remain asserted with all data inputs stable for a minimum of 50 nsec after the input is acknowledged by the FPIA signal. o The Front Panel Input Acknowledged (FPIA) signal is transmitted as an active low RS-423 (TTL) signal. It is asserted when input data has been loaded into the FIFO by the FPDR signal. Input data must and FPDR must remain stable for a minimum of 50 nsec after FPIA is asserted. FPIA will be de-asserted within 35 nsec after FPDR is removed.
CABLE ACCESS TRANSMITTER (CAT) Page 6-5 o J1 pin assignments are as follows: PIN FUNCTION PIN FUNCTION PIN FUNCTION A1 DATF+ B1 DAT9+ C1 DAT3+ A2 DATF- B2 DAT9- C2 DAT3- A3 DATE+ B3 DAT8+ C3 DAT2+ A4 DATE- B4 DAT8- C4 DAT2- A5 DATD+ B5 DAT7+ C5 DAT1+ A6 DATD- B6 DAT7- C6 DAT1- A7 DATC+ B7 DAT6+ C7 DAT0+ A8 DATC- B8 DAT6- C8 DAT0- A9 DATB+ B9 DAT5+ C9 LAM+ A10 DATB- B10 DAT5- C10 FPDR- A11 DATA+ B11 DAT4+ C11 FPIA- A12 DATA- B12 DAT4- C12 COMMON
184.108.40.206 J2 - Baseband Serial Output - J2 is a LEMO connector which outputs the encoded baseband SDLC message as a TTL signal. Output drive capability is determined by by the encoder circuitry connected to the CAT through J102. The Return To One Encoder (123-639-02) will drive 10 LSTTL loads. In general, this signal will be looped back into the J3 connector.
220.127.116.11 J3 - Baseband Serial Input - J3 is a LEMO connector which inputs a TTL signal and buffers it to the Phasecomp modem. It presents a 1 LSTTL load to the outside world. Typically this will be driven from the J2 Baseband Serial Output, but any TTL signal input will be passed along to the modem.
18.104.22.168 J4 - RF Output - J4 is a BNC connector connected to the output of the Phasecomp modem.
22.214.171.124 J101 - Connector to the Phasecomp Modem - J101 connects the CAT to the Phasecomp modem, providing power, control, and data to the RF transmitter and receiving status. The interface generally corresponds to RS-449 (differential RS-232). Of the 40 pins in the connector, only the following are used:
CABLE ACCESS TRANSMITTER (CAT) Page 6-6 PIN FUNCTION 4 GND 5 +12 6 TXD+ 7 TXD- 12 RTS- 13 RTS+ 16 CTS- 17 CTS+ 26 GND 27 +12 30 GND 31 +12 32 GND 33 +12
126.96.36.199 J102 - Baseband Encoder Interface - J102 is a 14 pin DIP socket allowing an interface to baseband encoding circuitry. Pins are assigned as follows: PIN FUNCTION 14 +5 13 +5 12 TxSO From the MPCC. Drives 4 LSTTL loads. 11 TxC To the MPCC. 1 LSTTL load. 10 TxE MPCC control line. Drives 5 LSTTL loads. 9 TxA From the MPCC. Drives 1 LSTTL load. 8 --- 7 GND 6 GND 5 SDLC OUTPUT Connects to J2 4 1 MHz CLOCK Drives 5 LSTTL loads 3 2 MHz CLOCK Drives 5 LSTTL loads 2 4 MHz CLOCK Drives 5 LSTTL loads 1 8 MHz CLOCK Drives 5 LSTTL loads.
6.4 FRONT PANEL DESCRIPTION
6.4.1 Connectors o J1 - This connector mates to the standard SLC 36-conductor cable. Sixteen pairs are used to differentially encode data to be transmitted, one line is used to encode a 'LAM' bit, two lines are used to manage the handshake of writing to the CAT, and one line is defined as common. o J2 - This LEMO connector makes available the baseband encoded SDLC message.
CABLE ACCESS TRANSMITTER (CAT) Page 6-7 o J3 - This LEMO connector accepts TTL data and, after passing it through a differential driver, presents it to the modem. o J4 - This BNC connector makes available the RF output of the modem.
6.4.2 Status LED's o MODEM POWER - +12V to the modem. o MODEM CARRIER ON - The modem is transmitting. o N - Camac N line stretched by a one-shot. o FPE - Front Panel Input is enabled. o FPIA - Front Panel Input Active acknowledges the receipt of data through the front panel. Stretched by a one-shot. o IRED - FIFO Input Ready. o ORED - FIFO Output Ready. o CTS - Modem Clear To Send. o XLOCK - The internal data bus is locked by an SDLC message transmission. Stretched by a one-shot. o POWER - +5V to the CAT.
6.5 DRAWING PACKAGE NUMBER 123-639
6.6 RESPONSIBLE ENGINEER E. Linstadt