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                52.1    GENERAL DESCRIPTION  . . . . . . . . . . . . . .  52-1
                52.2    FRONT PANEL  . . . . . . . . . . . . . . . . . .  52-1
                52.3    FUNCTIONAL DESCRIPTION . . . . . . . . . . . . .  52-2
                52.4    POWER SUPPLY REQUIREMENTS  . . . . . . . . . . .  52-3
                52.5    DRAWING PACKAGE NUMBER . . . . . . . . . . . . .  52-3
                52.6    RESPONSIBLE ENGINEER . . . . . . . . . . . . . .  52-4

                                      CHAPTER 52
                           SIMPLE TIMING BUFFER II (STBII)

        52.1  GENERAL DESCRIPTION

        The STBII performs three functions, one related to CAMAC  crate  power
        supply monitoring, and two related to the SLC timing system.  LED's on
        the front panel provide visual indication of CAMAC +/-6V,  +/-24V,  Y1
        (an additional -6V supply) and timing system upper backplane -2V (from
        the PDUII)  supplies  being  within  tolerance.   The  status  of  the
        tolerance  of  the  Y1  and  -2V supplies may also be remotely checked
        through the CAMAC interface, as the Crate Verifier  does  not  monitor
        these supplies.
        The STBII fans out to LEMO connectors on the  front  panel  NIM  level
        versions of all 16 channels of timing signals provided by the PDUII to
        the crate auxiliary upper backplane.  The 119 MHz clock  with  missing
        pulse  fiducial, received from the FIDO by the PDUII and placed on the
        upper backplane, is also brought out to the front panel.
        Timing measurements are also performed by  the  STBII.   The  time  of
        occurence of a pulse, relative to the fiducial, from any one of the 16
        PDUII channels, or from a NIM signal connected to the front panel  EXT
        HALT  input,  is  measured.  Edges in the 119 MHz waveform are used to
        increment a counter, so each count represents an interval of 4.2 nsec.
        The  measurement  may be gated by the appropriate occurrence of the PP
        or YY field received in the broadcast beam codes.
        When using the STBII to verify PDUII operations, remember  that  there
        will  be  a latency of 7 counts in the measurement, and that the PDUII
        is programmed in 8.4 nsec increments.  That is, if a PDUII channel  is
        programmed  to  output  a pulse at time N, the STBII will measure this
        pulse as occurring at time (2*N)+7.

        52.2  FRONT PANEL

              o  Single Width CAMAC Module
              o  LED's indicating crate +/-24V, +/-6V, Y1 = -6V and  Auxiliary
                 Backplane -2V supplies are within tolerance (+/- 5%)



        SIMPLE TIMING BUFFER II (STBII)                              Page 52-2

              o  16  LEMO  connectors  with  NIM  output  signals  from  CAMAC
                 auxiliary backplane channels 0-F.
              o  1 LEMO connector with NIM output signal from CAMAC  auxiliary
                 backplane 119 MHz.
              o  1 LEMO connector as NIM input to externally halt the interval
                 timer.

        52.3  FUNCTIONAL DESCRIPTION

              o  F(17)A(0) selects the  mode  of  operation  of  the  interval
                 timer.   Bits W1-W8 are compared with a selected field in the
                 PP/YY Pattern Input Registers.   When  a  match  occurs,  the
                 interval  timer  counter is started when the next fiducial is
                 detected.  Bits W9-W13 select which channel is used  to  stop
                 the  interval  timer  counter.   W9-W12  select  Ch0-ChF when
                 W13=0.  When W13=1, the EXT HALT input is used  to  halt  the
                 interval  timer.   Bits  W14-W16 select a PP or YY field from
                 the PP/YY Pattern Input Registers, for enabling the  interval
                 timer, as follows:
                    W16  W15  W14
                     0    0    0       F19 A8 W1-W8 (YY)
                     0    0    1       F19 A8 W9-W16 (PP)
                     0    1    0       F19 A9 W1-W8 (YY)
                     0    1    1       F19 A9 W9-W16 (PP)
                     1    0    0       F19 A10 W1-W8 (YY)
                     1    0    1       F19 A10 W9-W16 (PP)
                     1    1    0       Undefined (Time slot Info?)
                     1    1    1       Always generate a match. The interval
                                       timer will be started when the next
                                       fiducial is detected.
                         Q=1 and X=1 are generated in response to this command.
              o  F(1)A(0) R1-R16 reads back the mode select register  (F17  A0
                 W1-W16).  Q=1, X=1.
              o  F(1)A(1) R1-R8 reads back a byte from the PP/YY Pattern Input
                 Registers, as selected by F17 A0 bits W16-W14.  Q=1, X=1.
              o  F(9)A(0) resets the module.  Q=1, X=1.  The  module  is  also
                 reset on Z*S2.



        SIMPLE TIMING BUFFER II (STBII)                              Page 52-3

              o  F(27)A(0-3) return the following status as Q=1  (Will  always
                 return X=1):
                     A(0)  -  Y1= -6V +/- 5%
                     A(1)  -  Auxiliary backplane -2V  supply = -2V +/- 5%
                     A(2)  -  Interval measurement data is available
                     A(3)  -  Match condition - an interval measurement will
                              be started when the next fiducial is detected.
              o  F(19)A(8), A(9),  and  A(10)  are  the  PP/YY  Pattern  Input
                 Registers.    W1-W16  receive  the  pipelined  beam  patterns
                 (PP/YY), for enabling the interval measurements.  No Q  or  X
                 response is generated in response to these commands.
              o  F(0)A(0) R1-R24 reads out the  22-Bit  interval  timer.   The
                 interval  timer  starts  counting when a fiducial is detected
                 from the auxiliary backplane 119  MHz  signal,  and  a  match
                 between  the  PP/YY field of the mode select register and the
                 selected PP/YY Pattern Input Register exists.  Counting stops
                 when  the  selected channel is triggered.  The counting clock
                 is derived from edges detected in the 119  MHz  waveform.   A
                 Q=0  response  indicates that an interval measurement has not
                 been made.  The interval timer is  re-enabled  after  reading
                 out  the  interval timer [ F(0)A(0) ], or writing to the mode
                 select register [ F(17)A(0) ].  The interval timer is  halted
                 if  a stop pulse was not detected by a jumper determining the
                 maximum value of the counter.  For 360  Hz.   operation,  the
                 timer  will halt at a count of '10004B'H (corresponding to an
                 interval of 4.4 msec.), and for 180 Hz.  operation, the timer
                 will halt at a count of '20004D'H (an interval of 8.8 msec.).

        52.4  POWER SUPPLY REQUIREMENTS

        +24V @ 40mA
        -24V @ 40mA
        +6V @ 1.0A
        -6V @ 2.5A
        Y1 (aux -6V supply) @ 20mA

        52.5  DRAWING PACKAGE NUMBER

        233-001



        SIMPLE TIMING BUFFER II (STBII)                              Page 52-4


        52.6  RESPONSIBLE ENGINEER

        E.  Linstadt