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5.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . 5-1

5.2 CAMAC COMMAND DESCRIPTION . . . . . . . . . . . . 5-2

5.3 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . 5-4

5.4 TEMPERATURE . . . . . . . . . . . . . . . . . . . 5-5


5.5.1 J1 - Front Panel Parallel Data Connector . . . . 5-5

5.5.2 J2 - RF Input . . . . . . . . . . . . . . . . . 5-6

5.5.3 J101 - Connector to the Phasecomp Modem . . . . 5-6

5.5.4 J102 - Baseband Decoder Interface . . . . . . . 5-6

5.6 FRONT PANEL DESCRIPTION . . . . . . . . . . . . . 5-7

5.6.1 Connectors . . . . . . . . . . . . . . . . . . . 5-7

5.6.2 Status LED's . . . . . . . . . . . . . . . . . . 5-7

5.7 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . . 5-7

5.8 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . . 5-7 CHAPTER 5 CABLE ACCESS RECEIVER (CAR)

5.1 GENERAL DESCRIPTION The Cable Access Receiver (CAR) is a triple width CAMAC module whose RF Receiver demodulates a 2M baud serial bit stream. The serial bit stream is converted to a 16-bit wide parallel data word by a Synchronous Data Link Control (SDLC) protocol controller chip, and made available to either CAMAC or a front panel connector. The RF Receiver is manufactured by Phasecomp, and is described in the 'MODEMS' chapter as the 'Pattern Modem Data Receiver'. The companion transmitter module, the Cable Access Transmitter (CAT) is described in a separate chapter. Together, the CAT and CAR provide a high speed data communications link over the SLCNET cable that does not require processor intervention. The primary use of the CAR in SLC will be to receive beam timing information, patterns, and make it available to the sector microcomputers by way of its front panel interface and the Multibus based PRIM board. Upon application of power, or in response to a CAMAC initialization command (Z*S2, F9, or F11), a finite state machine implemented with an FPLS (Field Programmable Logic Sequencer) initializes a Multi-Protocol Communications Controller (MPCC) (Signetics SCN2652) as an SDLC secondary station which is waiting in receive mode. The secondary station address is set to 00H, but the CAR will also respond to broadcast (SSA=0FFH) messages. Serial data from the RF Receiver is processed by a daughter board which plugs into a 14 pin Dip Socket on the CAR. This daughter board recovers the receive data clock, convertsthe received baseband data to NRZ (Non-Return to Zero) format, and presents the receive clock and receive data to the MPCC chip. Return-to-One baseband encoding/decoding is required in the CAT and CAR to circumvent peculiarities of the Phasecomp modems. The CAR Return-to- One decoder board is described in the SLAC 123-640-02 drawing package. When a valid SSA is received, the logic sequencer in the CAR decodes bits in the control field of the SDLC message to generate a CAMAC LAM or 17th "interrupt" data bit. Other bits in the control field are reserved for the future implementation of multiword SDLC packets. The two data bytes of a pattern transmission are received and buffered, and then the received CRC Checksum is calculated and compared with the received value. If no errors were detected, the received data word is written into a 64 word FIFO buffer, a LAM is generated if it was received and enabled, and a 24-bit counter keeping track of the number of "good messages" received

CABLE ACCESS RECEIVER (CAR) Page 5-2 is incremented. Once the data has propagated through the FIFO and data has stabilized, a handshake line (ORED) is asserted on the front panel indicating that data is available to be read. If an error was detected in receiving the SDLC message, the following word is written to the FIFO (instead of the potentially incorrect receive data): 0FFXXH where XX denotes the error status as defined by the MPCC chip (see below), and a 24-bit "bad message" counter is incremented. In either case, upon finishing the reception of a message, the CAR waits for the next one. The "INT" or LAM bit propagates through the FIFO with its associated data word; LAM will not be deasserted until its associated word has been read from the FIFO. For ease in on-line diagnosis and trouble shooting, all registers within the CAR that may be written to are able to be read from by CAMAC, provided the internal data bus is not being used for the reception of a message.

5.2 CAMAC COMMAND DESCRIPTION FIFO Read F0 A0 or R17=Int A1 R16-R1 = DATF-DAT0 Q = 0 if no data is in the FIFO. LAM Counter is decremented if R17 = 1. LAM/INT F0 A2 or R8-R1 = number of words in FIFO with Counter Read A3 associated interrupt bits. Good F0 A4 or R24-R1 = # of good messages received. Messages Read A5 Bad F0 A6 or R24-R1 = # of bad messages received. Messages Read A7 SSA F0 A8 R8-R1 = MPCC Secondary Station Address Register Read Register (identical to F1 A12). Channel Status F1 A0 R8 = No interrupt bits in FIFO. R7 = FIFO input ready R6 = FIFO output ready R5 = Modem carrier detect R4-R1 = Receive Channel #; set by wire wrap jumpers on board. MPCC Status F1 A1 R8-R6 = 0 R5=RxE (MPCC Receiver Enable) R4 = FLAG ) As defined by R3 = RxSA ) the Signetics SCN2652 R2 = RxDA ) MPCC chip. R1 = RxA )

CABLE ACCESS RECEIVER (CAR) Page 5-3 MPCC Registers F1 A8-A15 *** NOTICE *** MINIMUM CAMAC CYCLE TIMES AND MAXIMUM SPECIFIED CHIP DELAYS DUE TO SCN2652 MODIFICATIONS MAKE IT IMPOSSIBLE TO GUARANTEE THE VALIDITY OF THIS DATA. DEVICE FUNCTIONALITY MAY BE CHECKED WITH A SLOWER CRATE CONTROLLER. THESE COMMANDS MUST NOT BE USED FOR ROUTINE MODULE DIAGNOSTIC PURPOSES. *** NOTICE *** R8-R1 = Contents of Signetics SCN2652 MPCC Registers. The only one of real interest is A12, the Secondary Station Address (SSA) Register. This is initialized to zero. A13 is the Parameter Control Register, which is initialized to and should always equal 90H. The 80H bit enables receiving broadcast (SSA=0FFH) messages, and the 10H bit places the MPCC into secondary station mode, requiring received messages to have the correct SSA. A8 is the receive data buffer, and A9 receive data status register, with bits assigned as follows: R8 = CRC Error R7-R5 = Residual Bit Count R4 = Receiver Overrun R3 = Received Abort Character R2 = Received End of Message R1 = Received Start of Message. These are not of general concern, but more information is available in the Signetics SCN2652 data sheet. LAM Test F8 A0 Q = 1 if interrupt bits are buffered in the FIFO. Reset F9,F11 Reset and reinitialize the CAR. FIFOs, good message counter, bad message counter, and SSA are reset to 0. LAM's are disabled. The MPCC is initialized as a secondary station waiting in receive mode. FIFO Write F16 A0A1 W16-W1 are written into the FIFO. A1 is written into the FIFO as the interrupt bit and increments the LAM counter. Q = 0 if no room in the FIFO. LAM/INT F16 A2A3 W8-W1 are written into the LAM/Interrupt
CABLE ACCESS RECEIVER (CAR) Page 5-4 Counter Write counter. Good F16 A4 Increments good message counter. Message Counter F16 A5 Resets good message counter. Bad F16 A6 Increments bad message counter. Message Counter F16 A7 Resets bad message counter. Write F16 A8 W8-W1 are written into the MPCC Secondary SSA Register Station Address identical to a F17 A12. Receiver F17 A1 W1 sets (=1) or resets (=0) the MPCC Enable Receiver Enable line. In general, hands off. F17 A8-A15 W8-W1 are written into the MPCC's registers. The only one you ever want to touch is F17 A12, which sets the secondary station, and an F16 A8 is suggested instead. It could be useful for troubleshooting, or for modifying the functionality of the module, to write to some of these registers. For more information on what the consequences of this would be, consult the Signetics SCN2652 data sheet. LAM disable F24 A0 Disables the CAR's LAM generation capability. F26 A0 Enables the CAR's LAM generation capability. X = 1 is generated for all of the above commands. Q = 1 is generated if the CAR is capable of performing the command, (i.e., reception of a message is not in progress) unless otherwise specified.

5.3 ELECTRICAL SPECIFICATIONS Power Supply Requirements o The CAR requires +6 volts at 1.25 amps. o The Phasecomp Modem requires +24 volts at 0.5 amps.


5.4 TEMPERATURE The CAR will operate as specified between 0 and 65 degrees Celsius.


5.5.1 J1 - Front Panel Parallel Data Connector o The J1 connector mates to the standard SLC 36 conductor cable. o 16 data bits are output as RS-422 (differential TTL) signals. They are stable approximately 25 microseconds before ORED is asserted. o The LAM or Interrupt Bit is output as an active low RS-423 (TTL) signal. It will be asserted at most 1.6 microseconds before the other data bits are available at the output of the FIFO. o The output ready (ORED) signal is an active low RS-423 (TTL) output asserted approximately 25 nanoseconds after the other output data is stable. It is deasserted at most 75 nanoseconds after the FPACK signal is received. o The Front Panel Acknowledge (FPACK) signal is received as an active low RS-423 (TTL) signal. It is pulled up to +5 volts by a 120 Ohm Resistor. The output ready line is deasserted at most 75 nanoseconds after the FPACK signal is asserted. Output data (and, if applicable, the LAM bit) will remain stable for at least 10 nanoseconds after FPACK is deasserted. FPACK must be asserted for a minimum of 35 nanoseconds. o J1 Pin Assignments are as follows: PIN FUNCTION PIN FUNCTION PIN FUNCTION A1 DATF+ B1 DAT9+ C1 DAT3+ A2 DATF- B2 DAT9- C2 DAT3- A3 DATE+ B3 DAT8+ C3 DAT2+ A4 DATE- B4 DAT8- C4 DAT2- A5 DATD+ B5 DAT7+ C5 DAT1+ A6 DATD- B6 DAT7- C6 DAT1- A7 DATC+ B7 DAT6+ C7 DAT0+ A8 DATC- B8 DAT6- C8 DAT0- A9 DATB+ B9 DAT5+ C9 INT- A10 DATB- B10 DAT5- C10 ORED- A11 DATA+ B11 DAT4+ C11 FPACK- A12 DATA- B12 DAT4- C12 GROUND


5.5.2 J2 - RF Input J2 is a BNC connector connected to the Phasecomp Modem.

5.5.3 J101 - Connector to the Phasecomp Modem J101 connects the CAR to the Phasecomp Modem, receiving data and Status from the RF Receiver and providing power to the receiver. The interface corresponds roughly to RS-449 (differential RS-232). Of the 40 pins in the connector, only the following are used: PIN FUNCTION 4 GND 5 +12 10 Receive data + 11 Receive data - 24 Carrier detect - 25 Carrier detect + 26 Ground 27 +12 26 GND 27 +12 30 GND 31 +12 32 GND 33 +12

5.5.4 J102 - Baseband Decoder Interface J102 is a 14 pin DIP socket allowing connection to baseband decoding circuitry. Pins are assigned as follows: PIN FUNCTION 1 Carrier Detect (CDET). TTL Status from the Modem. Drives 5 LSTTL loads. 2 Serial Data in (SDIN). TTL Data from the Modem. Drives 5 LSTTL loads. 3-7 Ground 8 RxC. Receive clock to the MPCC. Must drive 1 LSTTL Load. 9 RxSI. Receiver serial input to the MPCC. Must drive 1 LSTTL load. 10-14 +5.



5.6.1 Connectors o J1 mates to the standard SLC 36-conductor cable. Sixteen pairs are used to differentially output the received data. One line is used to output the 'LAM' bit, two lines are used to handshake the reading of data from the CAR, and one line is defined as common. o J2 - This BNC connector brings the RF signal into the CAR.

5.6.2 Status LED's o MODEM POWER - +12V to the modem. o CARRIER DETECT - The modem hears a transmitter. o RxA - The MPCC is receiving a message. Stretched by a one-shot. o SHIFT IN - Data is being shifted into the FIFO. Stretched by a one-shot. o IRED - FIFO input ready. o ORED - FIFO output ready o SHIFT OUT - Data is being shifted out of the FIFO. Stretched by a one-shot. o N - CAMAC N line. Stretched by a one-shot. o LAM - The module is generating a CAMAC LAM.



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Contact (until Aug. 15, 1996): Jeffrey Miller
Owner: Bob Sass

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