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47.1 GENERAL SPECIFICATION OF THE MODEM. . . . . . . 47-1
47.2 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . 47-2
47.3 TRANSMITTER SPECIFICATIONS . . . . . . . . . . . 47-3
47.4 RECEIVER SPECIFICATION . . . . . . . . . . . . . 47-4
47.5 COMMAND (I\O WRITE TO ADDRESS 0400H) . . . . . . 47-4
47.6 STATUS (I/O READ FROM ADDRESS 0400H) . . . . . . 47-4
47.7 GENERAL DESCRIPTION OF COMPUTROL BOARD . . . . . 47-5
47.7.1 Relevant Documentation . . . . . . . . . . . . 47-6
47.8 GENERAL DESCRIPTION OF CMIB . . . . . . . . . . 47-6
47.8.1 CIRCUIT DESCRIPTION . . . . . . . . . . . . . 47-6
47.9 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 47-7
47.10 RESPONSIBLE FIRMS . . . . . . . . . . . . . . . 47-7
47.11 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 47-7 CHAPTER 47 SLCNET DATA MULTIBUS MODEM (SDMM) The SDMM provides a high speed (FSK) data transmitter-receiver combination for the SLCNET system used as the communications link between the sector micros and the VAX. It consists of two Multibus boards with a private connection made by means of a cable and plug-in daughter board. One board contains a Coherent Systems FSK Modem and the other is a Computrol Multibus Megalink board. The interconnection is made by the the Computrol Modem Interface Board (CMIB).
47.1 GENERAL SPECIFICATION OF THE MODEM. o Power Requirements: +12, -12, and +5 VDC from Multibus. o Size/Mounting: Multibus - Double Width. o Temperature: 0 C to 50 C Ambient. o Humidity: 10 to 90% Non-condensing. o Data Signals Provided: TxD, RxD, CD, and RTS as differential RS-422. o Control Signalling: Per Multibus spec. Intel manual #9800683-03. o Connectors: RS-422 Data 3M 3429-1302 26 contact. (J1) PIN FUNCTION PIN FUNCTION to CMIB 1 GROUND 14 GROUND 2 RxD+ 15 RxD- 3 GROUND 16 GROUND 4 CD+ 17 CD- 5 GROUND 18 GROUND 6 GROUND 19 GROUND 7 GROUND 20 GROUND 8 RTS+ 21 RTS- 9 GROUND 22 GROUND 10 TxD+ 23 TxD- 11 GROUND 24 GROUND
SLCNET DATA MULTIBUS MODEM (SDMM) Page 47-2 12 GROUND 25 GROUND 13 GROUND 26 GROUND Control Card edge - Multibus P1. RF Type BNC. Power Card edge - Multibus P1. o LED Indicators: Receiver oscillator Locked Transmitter oscillator Locked Request to Send Carrier Detect o TX-RX Offset 156.25 MHz.47.2 ELECTRICAL SPECIFICATIONS o Multibus I/O base address of card is 0400H, selectable by jumpers. o Data bits are used in a read/write register as follows: o D0 Transmit frequency control. - 0 = higher frequency (67 Mhz) - 1 = lower frequency (61 Mhz) o C1 Receiver frequency control. - 0 = higher (223.25 Mhz) - 1 = lower (217.25 Mhz) o D2 Transmitter frequency phase lock loop status. - 0 = locked (if loop not locked, unit can't transmit - wire wrap option). o D3 Receiver frequency phase lock loop status. - 0 = locked. o D4 Analog I.F. loopback control from 422. - 0 = normal
SLCNET DATA MULTIBUS MODEM (SDMM) Page 47-3 - 1 = loopback (Tx disabled) o D5 Digital loop back control from 422 port and RF loopback control from cable (wire-wrap option). - 0 = normal - 1 = loop o D6 Control of Frequency: - 1 = installed = switch control. - 0 = Not Installed = software control. (These override D7.) o D7 Frequency control selection: - 1 = Manual switches - 0 = Software control NOTE: D7 powers up in "1" state. The switch settings then initialize D0, D1, D4, and D5.47.3 TRANSMITTER SPECIFICATIONS o Modulation Type: Phase coherent FSK. o Modulation Rate: DC to 2 MHz. o Transmit Frequency: Software or hardware selectable (61.0 or
67.0 MHz). o Frequency Stability: +/- 50 KHz. o TX Freq Change Time: 200 msec max. o Output Level (on): +35 to +55 dBmV adjustable. o Output Level (off): -65 dBc.
SLCNET DATA MULTIBUS MODEM (SDMM) Page 47-4 o Spurious Outputs(off): 60 dB below max output. o Bandwidth: <= 6 MHz (Saw Filter). o RTS to Data Delay: 10 microsec minimum.47.4 RECEIVER SPECIFICATION o Sensitivity: -10 dbmv for 1 x 1E-8 error rate (C/N min 24 decibels for 6 MHz bandwidth). o Receiver frequencies: 217.25 and 223.25 MHz. o Hardware settable and optionally software settable. o Tx-Rx offset 156.25 MHz. o RTS (Tx) to CD (Rx) on/off time 2.5 microseconds maximum or less. o Pulse jitter from Tx to Rx < 20 nanoseconds at -10 dbmv into receiver and C/N = 24 decibels worst case.
47.5 COMMAND (I\O WRITE TO ADDRESS 0400H) DAT0 - Transmit channel - 0 = 67 Mhz 1 = 61 Mhz DAT1 - Receive channel - 0 = 223 Mhz 1 = 217 Mhz DAT2 - not used DAT3 - not used DAT4 - Analog loopback - 0 = normal operation 1 = loopback DAT5 - Digital loopback - 0 = normal operation DAT6 - not used DAT7 - Mode select - 0 = Multibus control 1 = Local control
47.6 STATUS (I/O READ FROM ADDRESS 0400H) A status read returns all bits defined by the command byte in addition to the following:
SLCNET DATA MULTIBUS MODEM (SDMM) Page 47-5 DAT2 - Transmitter locked - 0 = frequency is locked. 1 = frequency not locked. DAT3 - Receiver locked - 0 = frequency is locked. 1 = frequency not locked. DAT6 - Local locked - 0 = capable of multibus control. 1 = locked in local control mode. o This mode inhibits the transmitter output and receiver VCO. The transmit data applied to the SD input is modulated by the transmitter at IF. The demodulated data is applied to the RD receiver alignment. It tests all circuity except the frequency converters. Channel selection, RS and CD are ignored in this mode. o This mode loops all data at TTL levels. Data presented to the SD input is looped and returned at the Rd output. Also, Rs is looped to RR. Demodulated data from the receiver is looped to the transmitter input. A jumper option allows transmitter operation with the presence of carrier from the receiver for repeater operation. This mode used both RF channels for repeater operation so caution must be used in this mode. Repeater operation can be disabled with a jumper option. Operation of analog and digital loopback simultaneously gives undefined results. Upon power up, the modem assumes local control from the switches. Multibus operation can begin by a write command with bit 7 reset.47.7 GENERAL DESCRIPTION OF COMPUTROL BOARD The Computrol board (Computrol Multibus Megalink Model 11-0080) is, in essence, a Multibus - SDLC (Synchronous Data Link Control) channel, allowing DMA transfers between Multibus memory and a 1 Megabaud serial data stream. The Computrol board, by means of SLAC developed firmware, the CMIB and the SLCNET Modems, allows the SLC Micro Cluster's Intel 86/30 single board computer to communicate with the VAX SLCNET Controller (VSC), forming the mainframe to micro link of the SLC control system. The Computrol board is accessed by the 86/30 at Multibus memory locations 0F0000H-0F03FFH. Writing to location 0F0400H interrupts the Computrol board, forcing it to examine the commands requested by the 86/30. Typical commands tell the Computrol board to write a given block of memory out over the SDLC channel, or to receive a block of data from the SDLC channel and place it at a given Multibus address. The Computrol board then interrupts the 86/30 when the requested
SLCNET DATA MULTIBUS MODEM (SDMM) Page 47-6 transfer has been completed. Special firmware running on the Computrol board ("Chocolate-Chip") allows the Computrol board to respond to poll requests from the VAX without interrupting the 86/30, increasing system throughput and greatly reducing the processer overhead associated with routine network communications.47.7.1 Relevant Documentation Computrol Multibus Megalink Model 11-0080 Instruction Manual Computrol Chocolate-Chip Documentation (in the SLC Software Lab) Computrol-Modem Interface Board (CMIB, SLAC 123-667)
47.8 GENERAL DESCRIPTION OF CMIB A special modem interface is required since SLCNET is not compatible with the modems Computrol normally uses with their board. Computrol's clock recovery circuitry is not compatible with SLCNET timing requirements. The CMIB also allows several Computrol boards to share a single modem. The CMIB is attached to the Computrol board through the 40 pin DIP socket on the Computrol board that normally holds the WD1933 SDLC chip. The SDLC chip is then placed in a socket on the CMIB. This allows the Computrol board to access the SDLC chip while isolating the RxC and RxD (Receive Clock and Data) signals from Computrol's hardware, and allowing easy access to the RTS and TxD (Request To Send and Transmit Data) outputs. The CMIB also obtains power (+5V) through this socket. Interface to the modem is accomplished by a 26 conductor ribbon cable. TxD and RTS are differentially driven by tri-state drivers, with the Computrol RTS signal enabling the drivers. Data is received as a differential signal from the modem, terminated by a 120 Ohm resistor. Daisy chaining of several Computrol boards which share a single modem is possible if the termination resistor is removed from all CMIBs except the last one (furthest from the modem) in the chain.
47.8.1 CIRCUIT DESCRIPTION RTS and TD come from the Computrol board, and are buffered by inverters. A D-Flip/Flop and an XOR gate are used to bring the TxD lines into a known state when asserting RTS. Asserting RTS also enables the tri-state drivers, passing TxD and RTS to the modem. Transitions in the received data stream shift data into a FIFO. Data is shifted out of the FIFO by an on board clock whose frequency is jumper selectable. The on board clock is resynchronized to the
SLCNET DATA MULTIBUS MODEM (SDMM) Page 47-7 received bit stream on alternate transitions in the bit stream by a D-Flip/Flop, provided that the transition has occurred within a time interval set by a retriggerable one-shot. This regenerates the receive clock and data with duty cycles and setup times as required by the SDLC chip.47.9 DRAWING PACKAGE NUMBER 120-021 (Modem) 123-667 (CMIB)
47.10 RESPONSIBLE FIRMS Coherent Systems Inc./ Computrol Corp.
47.11 RESPONSIBLE ENGINEER E. Linstadt.