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41.1 PHYSICAL . . . . . . . . . . . . . . . . . . . 41-1

41.2 FRONT PANEL . . . . . . . . . . . . . . . . . . 41-1

41.3 ELECTRICAL . . . . . . . . . . . . . . . . . . . 41-2

41.3.1 Input Stage . . . . . . . . . . . . . . . . . 41-2

41.3.2 Current Source . . . . . . . . . . . . . . . . 41-3

41.3.3 ADC . . . . . . . . . . . . . . . . . . . . . 41-3

41.3.4 Comparators and Trip Registers . . . . . . . . 41-4

41.3.5 Lock . . . . . . . . . . . . . . . . . . . . . 41-5

41.3.6 Test . . . . . . . . . . . . . . . . . . . . . 41-5

41.3.7 Trip Threshold . . . . . . . . . . . . . . . . 41-5

41.3.8 Milport 1553 . . . . . . . . . . . . . . . . . 41-5

41.3.9 Milport Address . . . . . . . . . . . . . . . 41-6

41.3.10 CMON . . . . . . . . . . . . . . . . . . . . . 41-6

41.3.11 Identification . . . . . . . . . . . . . . . . 41-6

41.3.12 Input Configuration . . . . . . . . . . . . . 41-6

41.3.13 Clear . . . . . . . . . . . . . . . . . . . . 41-6

41.4 ANALOG SECTION . . . . . . . . . . . . . . . . . 41-6

41.5 DIGITAL SECTION . . . . . . . . . . . . . . . . 41-7

41.5.1 RMIL-A . . . . . . . . . . . . . . . . . . . . 41-7

41.5.2 RLOCKC . . . . . . . . . . . . . . . . . . . . 41-8

41.5.3 RTESTA . . . . . . . . . . . . . . . . . . . . 41-8

41.5.4 RVTE . . . . . . . . . . . . . . . . . . . . . 41-9

41.5.5 RCMONB . . . . . . . . . . . . . . . . . . . . 41-9

41.6 MODULE CHECKOUT . . . . . . . . . . . . . . . . 41-10

41.7 CAMAC . . . . . . . . . . . . . . . . . . . . . 41-11

41.8 RESPONSIBLE ENGINEERS . . . . . . . . . . . . . 41-12 CHAPTER 41 RESISTIVE TEMPERATURE DETECTOR (RTD) The RTD module is a 16 channel CAMAC temperature measuring module with 4 wire input to each channel. The module senses 2 wire or 4 wire connections to the temperture sensor and auto switches to the correct measurement mode. The module supplies approximately 3mA to the sensor, an external resistor with known temperature coefficient of resistance, so that temperature is determined by measuring the resistor voltage. A comparator on each channel can be set by CAMAC command to trip at a specified temperature, and the trip status can be read in real time by a milport 1553 link to the host computer. An ADC scans the channels and stores the temperatures for CAMAC readout. The comparators trip status and a trip memory register can be read by CAMAC.

41.1 PHYSICAL The RTD instrumentation shall be implemented in a single wide CAMAC module. The module is divided into two general sections as follows. The top section titled "MPS" is the Machine Protection System (MPS) serial port interface. Two SLC standard AMP 36 pin connectors, J1 and J2, are used to interface 16 RTD channels. Each channel requires four pins because of the four- wire RTD system. Therefore channel one is assigned pin numbers A1-A4, channel two is assigned A5-A8, and so forth. Pins C11 and C12 in each connector are used for the connector identification signal input from the Cable Monitor (CMON)module.

41.2 FRONT PANEL The top lemo connector is an external trigger input. Three square LEDs are used for status. The top LED indicates that 1553 is active. The bottom left LED displays the CAMAC "N" signal, and the bottom right LED displays the single trip, indicating that at least one of the channels has tripped and that the status for that channel has not been read out.

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-2 Under the LEDs are the 1553 IN and OUT connectors, for daisy-chaining modules. The last in the series must have the "OUT" terminated. These are tri-axial connectors, Trompeter type BJ77. Two SLC standard AMP 36 pin connectors, J1 and J2, are used to interface 16 RTD channels.

41.3 ELECTRICAL Signal Input All RTD signal inputs shall be electrically protected as follows: +/-30VDC +/-100 volt lOOµS transients.

41.3.1 Input Stage An external temperature varying resistor, Rt, is connected by 2 wire, A and D, or 4 wire A, B, C and D to the RTD input. The module supplies approximately 3mA of current to Rt through R2, thus developing about 300-380mV. accross Rt depending on the temperature. In 2 wire mode this voltage is sent by the connection A to the op amp buffer U3B, and then through switch U1D to the optional track and hold amplifier U5 to the analog section output. In 2 wire mode inputs B and C are floating so they are pulled up to +5V by R12 and R13. This causes the output of U3C to be at +5V, turning on switch U1D as required. In 4 wire mode, A, B, C and D are connected to Rt. The voltage at C will be about 18mV which will cause U1D to turn off and V1C to turn on. The instrumentation amplifier formed by U3A, U3C, and U3D senses the voltage across Rt without the 2 x 18mV. additions caused by cable resistance, and transmits it through U1C to the channel output. There is a small offset voltage caused by the 250nA. current through R12 and R13. This results in a 25uV. increase in the measured Rt voltage, equivalent to an error of 0.O25 degree C. The voltage at input pin C, after inversion at U1B, is defined to be a digital signal, MODENN, and transmitted to the digital logic. NN=channel number, 0-15. MODENN=1 for 4 wire connection, O for 2 wire. The RTD may be used as a general purpose high precision voltage scanner. The operaional ampifiers are Analog Devices OP-497, a quad precision op amp integrated circuit. The stability and precision of the OP-497 is high; input voltage offset is less than 75uV, with a temperature coefficient of less than 1uV/degree C, and input current is less than 0.15nA with a temperature coefficient of 0.3pA/degree C (typically). Since the mode sensing current is 250nA and the reverse leakage of the protection diode is of the order of a few nA these

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-3 currents are the dominant source of error. To achieve the precision of the OP-497, the resistances R12 and R13 should be unloaded, and if necessary, the protecion diodes CR7-10. The OP-497s cost approximately $5 and are bipolar, reasonably rugged. The resistors R15-18 that form the instrumentation amplifier configuration have a tolerance of 0.1% and a resistance tempco of lppm/degree C. The common mode input voltage rejection is greater than 114dB, 5 x 10(+5). Therefore the gain of the instrumentation amplifier is equal to 1 with an error of a few parts in a thousand, and stable to a few parts in a million. This level of error and stability is also present in the analog path leading to the ADC, the multiplexer and ADC input amplifier. If the ADC is 16 bits, a resolution of 1 part in 65,536 is available, approximately 15ppm. The ADC used for the non critical temperature monitoring appication is 12 bits, but pin compatible 14 and 16 bit ADCs are available and can be substituted, as the ADC memory and read out logic already have 16 bits capacity.

41.3.2 Current Source The current is supplied to the external temperature sensing resistor through R2, 3.24kohm 0.1% resistor. As this resistance is not infinitely large compared to the lOOohm temperature sensing resistor it is not a true currrent source and the effective temperature coefficient of resistance is reduced by 6% at O degrees C (or wherever external R=lOOohms), by the paralleling effect of the external and internal resistors. Also, a slight non-linearity is introduced, so that the 6% decrease in the R temperature coefficient at O degrees C becomes 7% at 50 degrees C. The temperature coefficient of the external R, 394mohm/degree C, then is reduced to 371mohm/degree C at 0, 366mohm/degree C at 50 degrees for the combined resistors. If a linear fit is made to the resistance versus temperature curve with an effective temperature coefficient of 368.2mohm/degree C, and calibrated at 21 degrees C, then the temperature error due to non-linearity is less than .05 degrees C for temperatures 21-50 degrees, and less than 0.1 degree for 0-21 degrees, i.e. negligible. The change in voltage with temperature is : (368mohm/degree C)(3mA current) = lmV/degree C, approximately.

41.3.3 ADC The ADC has 12 bit resolution, spanning a 1V range with 4096 counts, approximately .25mV per count; so each count = .25 degrees C. The ADC can be set to scan free running, or to be triggered by setting a switch accessible through a hole in the side cover of the module. The required trigger is a NIM signal, with at least 25nsec duration, connected by front panel LEMO input. The input resistance is 20kohms,

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-4 so one signal can trigger several modules connected in series using a front panel T, with the last module terminated in 50 ohms. Track and hold amplifiers are optionally installed on each channel. They are set to HOLD by the trigger and reset to TRACK when the ADC scan is completed. These amplifiers will not be loaded for RTD use of this module, mince they are a source of slight voltage error and unreliability, and have little merit for measuring a signal that requires seconds to change significantly. There may be later applications of this module that require a time strobe. There is no provision for a BUSY signal in the SLAC CAMAC sytem, so consideration must be given to data errors due to bus collisions. To reduce errors the ADC conversion data are stored in alternate memory buffers for sequential scans. If a CAMAC ADC read is made during an ADC conversion, the present scan is halted, and the data is read from the memory buffer storing the data from the previous scan, made about 300msec earlier. After an ADC read, Q=0 for reads, until a second scan has been completed. To scan the 16 channels requires 2.74msec, with a 300msec interval between scans in the free run mode. If the triggered scan is used, then scan times can be set to avoid the times of CAMAC reads.

41.3.4 Comparators and Trip Registers Each of the channels has a comparator to sense temperatures above a CAMAC set threshold to set an alarm, the TRIP register. All 16 TRIP registers outputs go to an OR, its output drives a front panel LED through a pulse stretcher, so that even a momentary over temperature will produce a visible LED flash. Each threshold is set by 12 bit DAC. The 4096 DAC counts cover a 4V range, approximately lmV per count, equivalent to 1 degree C per count, in the setting of the comparator threshold. The comparator voltage drift is less than 2OuV so it can be neglected. The comparators can be read out by a 1553 port and by CAMAC read. The comparator output sets the TRIP register, a SET-RESET register. There are two CAMAC read commands: the comparators can be read directly, or the TRIP register can be read with an automatic RESET following the read. Thus, a momentary temperature excursion above the comparator threshold will not be detected by a later 1553 or CAMAC read of the comparators, but will be detected by a later read and reset of the TRIP register. If the temperature is still above the comparator threshold, the TRIP register will be set again as soon as RESET ends. Q=1 for both comparator and TRIP register reads.


41.3.5 Lock Each channel can be individually locked, and the module has also a global lock, which must be set for the channel locks to be effective. No changes can be made to the milport 1553 address or to the channel lock settings while the global lock is on. The global lock also inhibits the CLEAR command, see section 13 below. Thus, to set channel locks the global lock must be turned off, the desired channel locks set, and then the global lock turned on again, to make them effective. Q=1 for setting or reading the channel lock status unless the global lock is on, in which case the channel lock status will not change, and Q=0 will respond to the channel lock command. Channel locks on prevent action of the test and trip threshold set commands.

41.3.6 Test A test switch, U1A, Figure 1, can be set on each channel, which increases the source current by 10%. This will result in a 10% increase in the resistor voltage, 30mV or more, equal to 30 degrees C for a nominal 100 ohm temperature sensing resistor. Q=1 for loading or reading the 16 bit test register, unless any of the channels is locked. Then, for load commands only, Q=0 as a warning to the operator to verify that the channel that is to be changed is unlocked.

41.3.7 Trip Threshold The trip threshold can be set by loading a 12 bit DAC for each channel. The DAC setting can be read back. Q=1 for loads and reads, unless a channel is locked. In the threshold set logic the channel being set is identified, so unlike the test logic, Q=0 unambiguously signifies an attempt to change a locked channel. It is a failure, not a warning.

41.3.8 Milport 1553 The milport 1553 reads back four 16 bit words. The first is formed of the channel trip status bits, channel O in the least significant bit, channel 1 the next bit, and so on. The second word is a repeat of the first word. The third and fourth are test patterns, 5555 and AAAA(hex), respectively. The serial read order is least significant word first, most significant bit first.


41.3.9 Milport Address The five bit milport 1553 address is loaded via CAMAC, and the address can be read back. Q=1 unless the global lock is on, in which case Q=0 for loads, signifying failure.

41.3.10 CMON Input cables can be identified using the CMON logic. There are separate CAMAC read commands for each of the two input cables. Q=1 always.

41.3.11 Identification A 16 bit identification word can be read by CAMAC. The high 8 bits = 42(hex), to identify the module as an RTD; the lower 8 bits = the serial number of the individual module. Q = 1 always.

41.3.12 Input Configuration The input configuration, 2 or 4 wire, sets the MODE bit for each channel, as described above in section 1. The 16 bits are read by CAMAC F2A15, with Channel O MODE being the LSB. Q=1 always.

41.3.13 Clear A clear command can be sent via CAMAC, and will execute if the global lock is off. This sets to O the trip, lock, and test registers and sets the comparator trip threshold voltage to 0. The milport 1553 address register is set to 11111, i.e. 31. Q=1 if the global lock is off. Q=0 if the global lock is on, signifying that CLEAR did not execute.

41.4 ANALOG SECTION There are two schematics for the analog section, the first for channels 1-8 and the second for channels 9-16. SD-125-750-01. These

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-7 schematics show the analog circuit for each channel, plus the lines to the input connectors. These schematics are fully detailed presentations of all the channels with the circuit of Figure 1 repeated.

41.5 DIGITAL SECTION The digital schematic, also SD-125-750, has several major components: the power supplies, the 1553 port, the Xilinx fpga's which contain most of the digital logic, the PROMs which configure the fpga's at power on, the DACs which set the comparator thresholds, the comparators, the ADC and its ancillary circuits, and the line driver/receivers which buffer the fpga's from the CAMAC backplane. There are 2 major data buses in the digital area. Bus A is 16 bits and links the ADC, the ADC memory, the DAC registers, CAMAC read and CAMAC write buffers. Its functions are to allow the ADC to write to ADC memory, to read the ADC memory through CAMAC, to write through CAMAC to the DACs, and to read the DACs through CAMAC. Since the same bus is used for read and write, and since CAMAC commands may interrupt an ADC read to its memory, there must be appropriate gating of all of the above bus users to reduce the effect of conflicts. Bus B is 32 bits, 16 read and 16 write, from the CAMAC buffers to the 2 fpga's. An additional bus, the CAMAC bum sends the CAMAC command elements to the fpga's, the N, F's, A's, S1 and S2, and returns the handshake X and Q signals. Fpga 1, U86, contains the logic for the DAC read/write, 1553 milport address, test, lock and ID word logic. The documentation package for the RTD contains schematics for the fpga logic. For fpga 1 there are 5 schematics. The root schematic is RTDX1X, where the final X indicates the version, ranging from A to Z, presently X=Q. RTDX1Q contains the pin assignments of the IC which match those shown in the digital schematic. It also shows the connection of the pins to signals connected to 4 internal schematics, which cover the 1553 address, the test, lock and DAC logic. The root schematic may contain some small logic which is not extensive enough to require its own schematic. For fpga 1 the logic that sets the ID word, the MODE lines, the multiplexers which direct the appropriate outputs of the internal logic blocks to the CAMAC read lines, and some ORing of Q s from the various sublogic blocks is contained on the root schematic. The internal schematics of RTDX1Q are, at this time, RVTB, RTESTA, RMILA-, and RLOCKC, where the final letter indicates the version.

41.5.1 RMIL-A This logic covers the CAMAC command to set and read the address of the 1553 port (colloquially, the milport). The commands write, F17A11,

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-8 and read, FlA11, are inputs to fpga 1; S1 is the CAMAC S1, and /GLOLOCK is the global lock command, with the preceding / indicating negative=true logic. The AND of F17A11' S1, and /GLOLOCK at U329 clocks the 5 bit register U315319 which then loads the address presented on the CAMAC write lines, wl-w5. The data is inverted after each register bit so that the clear command to the register, CLRMA, which sets each bit to O per the hardware configuration of this register type, will set the output address to 11111, per the module specification. The inverter at the regiser input causes the register to load complementary data, which is inverted again by the output inverter so that the output 1553 address is the same as the write line data. The AND OR logic of U326 and U327 generates QMIL, the Q response of this logic, if there is a read, FlA11, or a write, F17A11, with the global lock. Off. The 5 address bits, MILAO-MILA4, return to the root schematic which shows their pin assignments and their multiplexer connection to the CAMAC read lines. The digital schematic will show their connection from fpga 1 pins to the 1553 fpga.

41.5.2 RLOCKC The lock register is 16 bits, one for each channel. F17A12 AND S1 AND /GLOLOCK load the 16 bit register. LKRn, n=1-16, is returned to the root schematic to the CAMAC read multiplexer, and then LKRn AND GLOLOCK, inverted, genertate fLKn, which is returned to the root schematic to be used to lock individual channels in the TEST and VT (comparator thresholds) logic. Note that GLOLOCK must be off to change the lock register, then on for the individual locks to be effective. U431 and U470 generate the Q response to lock commands. Clear will reset the lock register to 0. There is logic in fpga 2, discussed below, that prevents a clear command from executing if the global lock is on.

41.5.3 RTESTA The test logic is composed of a 16 bit register, one bit per channel which is set by F18A14S1 acting on each bit after being ANDed with /Lkn, the lock bit for the channel. The outputs of the register, TESTO-TEST15, are connected to output pins and the CAMAC read multiplexer, as shown in the root schematic. If any of the channels is locked, no Q signal is returned with the Fl8A14 write command, as a warning. F2A14 returns Q=1 regardless of lock settings.


41.5.4 RVTE RVTE shows the logic which controls the writing and readback of the 16 DACs whick set the threshold voltage for an over temperature trip for each channel. The DAC.s are external to the fpga and each has its own data register. They are packaged 4 per IC in 4 ICs, so the appropriate 1 of 4 chipselect commands has to be generated, and 2 address bits must be set on the selected DAC. to write or read the desired channel. CAMA1, CAMAC2, CAMA4, and CAMA8 are the 4 CAMAC address lines. To write to a DAC the CAMAC address is decoded into the 1 of 16 addresses needed and then individually ANDed with the write command, F21, and the channel lock. If the lock is off the Q return, QVTn, is generated. This output signifies an allowed write command to channel. These are ORed together in groups of 4 to generate the chip select, /CSDACj, j=1-4. S1 is ANDed in to set the timing. The 2 least significant CAMAC address are sent directly to the DAC ICs to address the appropriate channel of the 4 within the DAC IC, as shown in the digital schematic. /F21 is sent directly from the CAMAC logic in fpga 2, see below, to set the /WE control on the DAC. A DAC read command, F5An, is executed by ANDing F5 with the 2 MSB CAMAC addresses and ORing this into the /CSDACj logic of the write command. Since all 4 combinations of the 2 least significant CAMAC addresses are used in 1 IC, there is a unique IC addrems formed by the 2 most significant CAMAC addresses for each DAC IC. The /WE control on the DAC will be high (readback) by default, so the start of the iCSDAC] will cause the DAC IC to place the selected channel register contents on Bus A. All the QVTn and F5 are ORed together to generate the Q return for the threshhold set logic. Fpga 2 contains the logic to decode the CAMAC commands,RCAMI, the trip status registers, RSTATF, the cable monitor logic, CMONB, and the control logic for the ADC scan of the 16 channels, RADCP. The root schematic, RTDX2K, contains the above schematics, and, as with fpga 1, the read line multiplexors and controls, and the pin assignments for the I/O signals.

41.5.5 RCMONB The 16 inputs, 4 pins each, are connected to the module with 2 multipin connectors. To allow remote checking that the correct cable is connected, pins 35 and 36 carry differentially repeated pulse train identification signals of 1-31 pulses. The RCMON logic shows the 2 channels A and B for the 2 connectors. CMONA, the pulse train for connector A, iB counted in scalers U370 and U374. The beginning of the pulse train triggers 2 external MMVs, one,TO-A, with a period somewhat longer than the pulse train maximum time, one, DEADA, with a long period, much longer than the interval between pulse trains, so that if the system is active it is

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-10 retriggered while on, and so remains on. At the end of the pulse train the trailing edge of TO-A loads the scaler contents into register U371 and U372, and resets the scalers. The process is repeated with each pulse train unless DEADA turns off. Then the register is reset until DEADA returns to on, and new pulse trains are counted and loaded into it. The same logic is repeated for connector B. The outputs of the two registers are returned to the root schematic where they are connected to the CAMAC read multiplexer.

41.6 MODULE CHECKOUT To repair or check a module in unknown condition the following steps will lead to identification of faults: 1. Plug the module into a CAMAC crate test station and check commands manually as follows. (An auto test program is being written which will give an immediate diagnostic report.) 2. Send command F3AO, which should return the ID number, 43NN(HEX), where NN is the individual module serial number. If 43NN returns then +5 power is OK and the logic in Xilinx fpga 1 and 2 is OK. The module is alive. If there is an improper return check that power, +15, -15, +5, -5, +10, are present. If yes, then reset module by cyclin~ power or pushing the RESET button on the front panel, and observe pin 121 of the Xilinx fpgas. If the Xilinx configures properly from its PROM, there will be a burst of clock pulses about 55msec. long, about 250msec after RESET is initiated. If there is no burst of clock pulses, then the Xilinx is not configuring. Check for proper operation of the DATA IN fron the PROM to the Xilinx, Done/Pgm, Reset. These lines, with the clock line, control the configuration. If they are not shorted or open, then replace PROM or Xilinx IC. If there is a clock burst, then send a stream of F3AO commands, observe the CAMAC F, N, A, S1, S2 inputs to the Xilinx 2. They are decoded by Xilinx. 2 to generate an F3AO which is sent to Xilinx 1 where the 43NN word is stored. Xilinx 1 should send 43NN. Observe the CAMAC read lines at Xilinx 1 and trace the signals through the buffers to the CAMAC back plane. If improper signals appear at the Xilinx output check for shorts or replace the Xilinx IC. Occasionally single pins have failed, presumably due to ESD damage. Once the Xilinx s are working and the 43NN readback is seen the module is basically working, and other defects can be found relatively easily by exercising the appropriate CAMAC command and signal tracing.

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-11 If 100-20O ohm resistors are plugged into the signal connectors the ADC can be read out tc, confirm operation of the 16 channel amplifiers and of the ADC and its multiplexer. The module will source 3 mA into the resistor, so a DVM can be used to observe the proper voltage accross the resistor and through the input amplifiers, mux, and ADC. Test resistors can be 2 or 4 wire connected to the module input to check the different amplifiers for 2 or 4 wire inputs, and to check the auto switching from 2 to 4 wire mode. The trip levels can be checked by loading trip levels above and below the voltages present due to the resistor plugs. The TEST command can be checked with the ADC. It should increase the reading by about 500 counts (500 mV) or more, depending on the source resistance connected to the channel input. Lock can be checked by locking channels and attempting to change trip levels or to turn on/off test input to that channel. The milport address cannot be changed unless global lock is off. The milport readout requires a milport test station to test. See John Truebenbach. The CMON can be tested by putting pulse trains of 0-31 pulses into each CMON input and verifying the correct CAMAC readback.

41.7 CAMAC Summary of Camac Commands for the RTD 1. FOAO. Read the trip comparators. Ch 1-16 on R 1-16. Trip = 1. 2. FlA11. Read the Mllport address. R!-R5 3. FlA12. Read the individual channel locks. Ch 1-16 on R1-16. Locked = 1. 4. FlA14. Read cable monitor for J1, Ch 1-8. 5. FlA15. Read cable monitor for J2, Ch 9-16 6. F2AO. Read and reset the channel trip register. Ch 1-16 on R 1-16. Trip=1 7. Read test register. Ch 1-16 on R 1-16. Test = 1. 8. Read mode register. Ch 1-16 on R 1-16. 4 wire = 1. 2 wire = 0 9. Read module identification. Readback is 42NN(hex). NN = module serial number. 10. F4A(x). Read ADC, channel temperature. 11. F5A(x). Read DACs that set the trip levels.x=0-15 for Ch.1-16. Rl(lsb)-R12. 12. F9AO. Reset

RESISTIVE TEMPERATURE DETECTOR (RTD) Page 41-12 13. F17All . Write milport address. Rl(lsb)-R5. 14. F17A12 Write individual channel locks. W1-16 for Chl-16. 15. F18A14. Write channel software trip. W1-16 for Chl-16. 16. F21A(x). Write to DACs that set the trip level. x=0-15 for Chl-16. Wl(lsb)-W12. 17. F29AO. Unlock global lock. 18. F29A1. Lock global lock.

41.8 RESPONSIBLE ENGINEERS R. Chestnut, D. Hutchinson, R. Noriega, J. Olsen, J. Truebenbach

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