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38.1 INPUTS . . . . . . . . . . . . . . . . . . . . . 38-1
38.1.1 Timing Inputs . . . . . . . . . . . . . . . . 38-1
38.1.2 Front Panel "J9" . . . . . . . . . . . . . . . 38-2
38.2 OUTPUTS . . . . . . . . . . . . . . . . . . . . 38-3
38.3 CAMAC FUNCTIONS . . . . . . . . . . . . . . . . 38-3
38.4 POWER SUPPLY REQUIREMENTS . . . . . . . . . . . 38-4
38.5 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 38-4
38.6 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 38-4 CHAPTER 38 PROGRAMMABLE WIDTH UNIT (PWU) General Description The PWU is designed to receive the pulses generated by the Programmable Delay Unit (PDU) from the CAMAC upper backplane, and retransmit these pulses modified in width. Also received from the backplane is the 119 Mhz clock with fiducial. (Clock period is 1/119E6 = 8.4 nanoseconds.) The PWU ouptut pulse width can be varied in 8.4 nanosecond increments over the range of 1 to 2**20 clock periods (8.4nS to 8.8 mS). The PWU has 8 output channels which are selected from either the first or second group of 8 PDU channels via a Hard wire group select (pin J9) provided from the front panel. PDU Channels 0 thru 7, or Channels 8 thru F are available at the 8 front panel LEMO connectors. The output signals are standard NIM levels. The outputs are delayed by
8.4 nanoseconds plus logic delay from the backplane. Each output has a LED indicator, indicating that the appropriate channel has fired. Power-on or module reset will cause all delays to be set to 8 clock periods (8.4 nS). The leading edge of the OUTPUT PULSE is delayed by 1 clock period (8.4 nS), and there is a module dead time following the fiducial of approximately 2.2 micro seconds.
38.1.1 Timing Inputs The PWU uses the SLC upper backplane for the following signals: Signal Location Level ------------------ ------------- ---------------- 119 Mhz clock backplane differential ECL PDU pulse (16) backplane differential ECL
PROGRAMMABLE WIDTH UNIT (PWU) Page 38-2
38.1.2 Front Panel "J9" The front panel SLC connector contains jumpers and enable signals which regulate the generation of module outputs. The inputs are of three classes:
184.108.40.206 Channel block select: - The selection of which group or bank of 8 PDU outputs will be conditioned is determined by Pin A9 of J9. An open circuit will select the lower 8 PDU channels (Channels 0 thru 7) from the backplane. A short to ground will select the upper 8 channels (Channels 8 thru F). This information is software readable.
220.127.116.11 Channel Enable Control - For the purpose of beam containment and machine protection, each channel is gated by a variety of enable conditions. Each channel can either be gated by one of the two enables, or can be independent of the external enable inputs. Each of the 8 selected channels has two lines assigned for individual enable control (ENA(i) and ENB(i)). (Signal TRUE is TTL High or "open", FALSE is TTL Low or "short to ground"). The logic follows: ENB ENA (0 = TTL Low or Connected to ground) --- --- 1 1 = No enable. Output is inhibited. 1 0 = Channel (i) is enabled by (EN1) 0 1 = Channel (i) is enabled by (EN2) 0 0 = Channel (i) is always enabled. These signals are on J9 as shown: Ch # Pin #(ENA) Pin #(ENB) ---- ---------- ---------- 0/8 A1 C1 1/9 A2 C2 2/A A3 C3 3/B A4 C4 4/C A5 C5 5/D A6 C6 6/E A7 C7 7/F A8 C8
18.104.22.168 Channel Enable Signals - The enable/inhibit functions for each channel are be controlled via the 36-pin SLC front panel connector J9. There are two enable signals (EN1, EN2) that service all of the selected 8 channels. EN1 and EN2 are NIM levels. (Signal TRUE is -0.7 volts into 50 Ohms). These enable signals are presented to the connector J9 on pins A11:B8 and A12:B9.
PROGRAMMABLE WIDTH UNIT (PWU) Page 38-3
22.214.171.124 Connector Verification - "J9" also provides module (PWU) verification by presenting a shorted connection between Pins A10 and B10 of J9. The PWU will look for a shorted connection between Pins B11 and C11 to verify that the connector J9 is inserted. This information is software readable.
126.96.36.199 "J9" Connector Signal Table - Signal Location Level ------------------ ------------- ---------------- Active Return (EN1) A11 B8 NIM Signal. (EN2) A12 B9 NIM Signal. Block Select A9 Ground Ch 0-7 No Connection, Ch 8-F Pull To Ground. External Verification A10 B10 Pins are shorted. of module connected Internal Verification C11 B11 Module expects a short for module between these pins. Ch(i) enable ENA(i) A1-A8 Ground TTL or Short to Ground Ch(i) enable ENB(i) C1-C8 Ground TTL or Short to Ground Module Ground B1-B7
38.2 OUTPUTS There are 8 Programmed Width output signals, and a variety of LED indicators. Signal Location Level -------------- ---------------- --------- PWU pulses Front panel LEMO NIM level Pulse Present Front panel LED Block Select Front Panel LED "X" LIGHT Front panel LED
38.3 CAMAC FUNCTIONS The following CAMAC functions are supported:
PROGRAMMABLE WIDTH UNIT (PWU) Page 38-4 o F16 A(i) -- Load channel i with requested Width. The actual pulse width is (n+1) clock periods. Q=1 if the channel "i" is in the selected block of PWU channels. X=1. o F0 A(i) -- Read module width. Q=1 if the channel "i" is in the selected block of PWU channels. X=1. o F1 A0 -- Read status of front-panel channel enable jumpers. Q=X=1. The data is bit-encoded by channel, and is present as follows: Camac Line Bits Channel | Data State ---------- ----- ------- + ---- -------- R1-R2 0/1 0/8 | 0 Not Enabled R3-R4 2/3 1/9 | 2 Gated by EN2 R5/R6 4/5 2/A | 2 Gated by EN2 R7/R8 6/7 3/B | 3 Always Enabled R9/R10 8/9 4/C R11/R12 A/B 5/D R13/R14 C/D 6/E R15/R16 E/F 7/F o F1 A1 -- Read back cable status information. Q=X=1. R1 Block Select Jumper. 0 = Low Bank Selected. R2 Connector Verify. 1 = Verified. o Power On, F9 A0, Z -- Module reset. All outputs are set to 8 clock periods. Q=X=Undefined.
38.4 POWER SUPPLY REQUIREMENTS *** Not yet supplied ***
38.5 DRAWING PACKAGE NUMBER 135-734
38.6 RESPONSIBLE ENGINEER W. Pierce