[SLAC Controls Software Group [SLAC Controls Department] [SLAC Home Page]

Go to bottom of page

33.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . 33-1




33.5 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 33-3


33.1 GENERAL DESCRIPTION The PRIM is a Multibus board designed to allow bus masters to interrupt other bus masters. Programmable Interrupt Controller (PIC) circuits (Intel 8259A) are used to handle all the bus vectored interrupt "handshaking." There are eight possible interrupt inputs to each PIC. One PIC is used now, expansion to four PICs is possible. Jumpers allow the signal from the PIC to be routed to any unused multibus interrupt line. Three other signals produced on the board may be routed to a PIC input or multibus interrupt line. These signals are: o A CAMAC interrupt (CINT) produced by a crate controller LAM status output. o A valid pattern received (VPAT) interrupt. This is asserted when the data word received from the CAR has a most significant byte not equal to 'FF'H o An error pattern received (ERR) interrupt. This is asserted when the data word received from the CAR has the most significant byte equal to 'FF'H The board also provides a means of performing a multibus INIT remotely and locally. Remote INIT is produced when the data word received by the PRIM from the CAR is equal to 'FFFF'H or a special multibus I/O location (0206H) is addressed. A local INIT is produced by a pushbutton on the edge of the PRIM. The PRIM also decodes a multibus I/O address (0204H) to read a jumper plug installed on the back of the SLC MULTIBUS CRATE (123-631). This jumper plug provides the network secondary station address of the multibus crate, used by the SLCNET system for all data transfers. ______________________________ This Chapter is adapted from a memo by J. Nowak dated 3/11/83 and titled "Operational Description of the Pattern Receiver, Interrupt Multiplexer Multibus Board."


33.2 OPERATIONAL DESCRIPTION - INTERRUPT MULTIPLEXER The interrupt multiplexer gives any multibus master board installed in the system the ability to interrupt other multibus masters also installed in the same multibus crate. Vectoring and handshaking details are handled by an Intel 8259A Programmable Interrupt Controller (PIC) chip. Only one PIC is used. Each PIC has eight possible interrupt sources. Source and PIC selection is produced by decoding an eight bit data byte sent by the bus master requesting the interrupt. The byte is decoded as follows: Data bits 0-2 select the interrupt source (one of eight), bit 3 selects set (1) or reset (0), and bits 4-7 select which PIC is to be operated on (bit 4 set selects PIC # 1, bits 5 through 7 must be zero, as no other PICs are currently supported.).

33.3 OPERATIONAL DESCRIPTION - MISCELLANEOUS FUNCTIONS The PRIM also obtains input from a Cable Access Receiver (CAR), and a plug physically associated with the cluster installation location. The CAR transmits to the PRIM a 16 bit word representing the pattern information transmitted by the master pattern generator (MPG) micro. It may also transmit a data receiver error code or a cluster initialize command (FFXX or FFFF respectively). The multibus crate secondary station address is encoded in a plug permanently installed at the physical location of the crate. When this plug is installed in the multibus crate, its identity may be established. The plug information enters the PRIM via the P2 connector and is made available to the CMC by reading I/O location 204H. The CAMAC serial driver also provides an input to the PRIM. Any CAMAC crate controller can generate a LAM interrupt. This input may be wirewrapped to any PIC input.

33.4 DETAILED PRIM OPERATIONAL CONSIDERATIONS The board devices may be placed as a block of 64 addresses anywhere in the I/O 64K address space, by proper selection of jumpers. The default jumper places the first address of the block at 200H. The location 202H is where the pattern word (16bits) may be read. Reading this register resets the VPAT or ERR interrupt request flip-flop. The multibus crate location plug information may be read from I/O location 204H and a crate reset can be produce by writing to or reading from I/O location 206H. The PIC registers are addressed as follows: o PIC #1 - 220H, 222H

PATTERN RECEIVER INTERRUPT MULTIPLEXER (PRIM) Page 33-3 o PIC #2 - 224H, 226H ***not supported at this time*** o PIC #3 - 228H, 22AH ***not supported at this time*** o PIC #4 - 22CH, 22EH ***not supported at this time*** Another method of producing a multibus INIT is provided. If an all ones pattern is received from the CAR, the PRIM will produce a multibus INIT signal. Interrupt outputs from the PIC's may be routed to any of the eight "Multibus" INT signal lines or the multibus NMI interrupt line via jumpers. Jumpers are also provided for selecting when the ACK pulse is generated and for any valid pattern, pattern error, and CAMAC interrupt. Note: when connecting any of the interrupt signals to a PRIM interrupt input pin, the trace from the 8 to 1 data selector must be cut.


33.6 RESPONSIBLE ENGINEERS E. Linstadt/ A. Hunter/ J. Nowak

Go to top of page
Contact (until Aug. 15, 1996): Jeffrey Miller
Owner: Bob Sass

Converted from VAX Runoff output using doc2webset.pl