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30.1 PHYSICAL . . . . . . . . . . . . . . . . . . . . 30-1
30.2 FRONT PANEL . . . . . . . . . . . . . . . . . . 30-1
30.3 ELECTRICAL . . . . . . . . . . . . . . . . . . . 30-2
30.3.1 Signal Input . . . . . . . . . . . . . . . . . 30-2
30.3.2 ADC Trigger Input . . . . . . . . . . . . . . 30-2
30.3.3 Self Trigger . . . . . . . . . . . . . . . . . 30-2
30.3.4 Trigger Function . . . . . . . . . . . . . . . 30-3
30.3.5 Fast Integrator . . . . . . . . . . . . . . . 30-3
30.3.6 Slow Integrator . . . . . . . . . . . . . . . 30-3
30.3.7 Trip Thresholds . . . . . . . . . . . . . . . 30-4
30.3.8 Current Monitor . . . . . . . . . . . . . . . 30-4
30.3.9 MIL-1553B Interface . . . . . . . . . . . . . 30-5
30.3.10 Characteristics of Ion chamber System Assumed
30.4 CAMAC COMMANDS . . . . . . . . . . . . . . . . . 30-6
30.5 MIL-1553B INTERFACE . . . . . . . . . . . . . . 30-8
30.5.1 Simple Receive/Transmitter (SRT) MIL-1553B
30.5.2 Data Format . . . . . . . . . . . . . . . . . 30-9
30.6 RESPONSIBLE ENGINEERS . . . . . . . . . . . . . 30-9 CHAPTER 30 PROTECTION ION CHAMBER MODULE (PIC) The Protection Ion Chamber module is a double width CAMAC module designed to monitor five He and/or Ar-CO2 ion chambers. Three analog values are measured for each channel as well as four variable threshold digital signals. Front panel MIL-1553B connectors provide digital status to the MPS system.
30.1 PHYSICAL o five channels per module o double width CAMAC module with double printed circuit boards
30.2 FRONT PANEL o Input signal connector: BNC, 5 ea. o MIL-1553B Interface input connectors: 2 ea. Trompeter BJ77 in parallel o Trigger input connector: 2 ea. Lemo in parallel o LED's 1. 1 per channel, logical OR of the 4 trip latches in each channel 2. 5 ea. to indicate MIL-1553B port address 3. 1 to indicate MIL-1553B bus transfer (1 msec duration)
PROTECTION ION CHAMBER MODULE (PIC) Page 30-230.3 ELECTRICAL (All values marked with * have been calculated from component data sheet specs. They will be confirmed by test measurements when the devices are built.) (Some values are quoted in "[ ]" in units of Rads for convenient comparison. Such values assume one of the existing Argon filled ion chambers described below.
30.3.1 Signal Input o Protection: +/- 30 V. DC, +/-300 V. for 1 usec. o Maximum operating Input Current: 20 uamp. o Maximum single pulse input: 1 uC., if Iin is less than 1 uamp for the preceding 50 msec.
30.3.2 ADC Trigger Input NIM logic level, Rin greater than 10 Kohm. The last module in a chain should be terminated in 50 ohm. The input pulse width should be 20 nsec minimum width, 50 usec. maximum width. The external trigger should be set 100 usec prior to beam time. The self trigger will occur at beam time. The presence of an external trigger shall gate off the self trigger from the time of the external trigger until digitization is complete (approx. 3.7 msec) Given the circuit response to existing ion chambers, the effect of trigger timing variation on digitized signals is: o 211 ppm/usec for the Fast Integrated ADC o 11 ppm/usec for the Slow Integrated ADC @ 50 msec o <6 ppm/usec for integration times of 100, 500, or 1000 msec
30.3.3 Self Trigger Range: 1 uC. per pulse down to 1 nC. per pulse. Note that at the lower range the input signal must be free of interference which might generate false triggers. Since the module has resolution equal to 0.1 pC. per pulse, at 120 Hz. accelerator operation, it requires an external trigger per above for use with small pulses. Given the circuit response to existing ion chambers, the time slew over the dynamic range of the self trigger is <200 usec. This will result in a variance on pulse height of:
PROTECTION ION CHAMBER MODULE (PIC) Page 30-3 o 4.2% for the Fast Integrated ADC o 0.22% for the Slow Integrated ADC @ 50 msec o <0.11% for integration times of 100, 500, or 1000 msec30.3.4 Trigger Function The external trigger triggers the module 100usec before beam time. The HOLD command is delayed 1.6msec to allow the voltage of the fast integrator to reach maximum. The self trigger is delayed 1.5msec. Then the voltages of the 3 integrators on each channel are stored by generating the HOLD command to the track/hold amplifiers serving each of them. After a short delay the ADC scan is started. Note that the trigger is used only for digitizing amplitudes for CAMAC readout. It has no effect on trip evaluation.
30.3.5 Fast Integrator o Time constant: 2.5 msec. +/-10% o Maximum charge without saturation: 1 uC. -I/20., where I, in uamp, is the average signal current in the preceding 50 msec. o ADC precision: 16 bits. o Sensitivity: 2x15ppm of Qmax,=2x15 pC.,approximately, under most conditions, [=34 uRad. in Argon]. o Gain stability: 5x10(-3) (0-50 deg C) * o Pedestal stability: 30 ppm of Qmax (0-50 deg C) *
30.3.6 Slow Integrator This is the l.c., the least count. Gain Stability: 100 ppm (0-50 deg C, x20 scale) * Pedestal Stability: 13 l.c. (0-50 deg C, x20 scale) Resolution of Difference of Small Signals: If dTemp is less than 1 deg C. and dtime less than 1 minute between measurements then the module limits the precision due to 1/f noise, to about 1 l.c. or 15 pamp. The housekeeping current must be stable to the same level, which is approximately 10(-4) of the 100-200 namp normal current. o Time constant: programmable: 50, 100, 500, 1000 msec.
PROTECTION ION CHAMBER MODULE (PIC) Page 30-4 o Maximum current without saturation: 20 uamp.average, [79 kRad/hr in Argon]. o Maximum charge: same as the fast integrator. o ADC precision: 16 bits o ADC sensitivity: 1. (x1 scale): 15ppm of 20 uamp=0.3 namp.[=1.2 rad/hr.] 2. (x20 scale): 0.8ppm of 20 uamp.=15 pamp.[=.06rad/hr]30.3.7 Trip Thresholds o 4 comparators per channel, triggered by the slow integrator, x1 scale. o Threshold of each comparator is set by 12 bit DAC. DAC register can be read back by CAMAC command. o Sensitivity of threshold: 2.5 mV. ,= 5 nA. of signal, [20 Rad/hr in Argon]. o Threshold Stability (0-50 deg C):10 mV. o Thresholds are set by CAMAC command. Each comparator output sets a trip status latch. All comparator outputs can be read by CAMAC command. All trip status latches can be read/reset by CAMAC command. All comparator outputs can be read by the MIL-1553B interface. All comparators can be driven to trip level by a CAMAC generated test signal, which is latched. The test signal latches can be read back by CAMAC command.
30.3.8 Current Monitor Each channel is monitored for high and low current faults. o High current limit: 22 uamp. o Low current limit: 50 namp. o Minimum time to exceed high current limit or fall under low limit: 2 usec. o Current faults set separate latches for high and low faults, which can be read by CAMAC command.
PROTECTION ION CHAMBER MODULE (PIC) Page 30-5 o High and low fault latches can be reset by CAMAC command. o The high and low comparators are read by the MIL-1553B Interface.30.3.9 MIL-1553B Interface o Transformer coupled stub input conforming to MIL-1553B Standard. o Default MIL-1553B RT address = 11111(binary) on power up. o The port address shall be loaded into a 5 bit module register by CAMAC command.
30.3.10 Characteristics of Ion chamber System Assumed In This Spec o Ion chamber power supply: 300 V. o Ion Chamber voltage: 200 V. o Housekeeping Current: 100-200 namp. o Housekeeping and signal current polarity: negative. o Housekeeping Current Source Resistance: 10. Mohm. o Signal Cable: 1. length less than 1000 ft. 2. Capacitance less than 30 nF. 3. Characteristic resistance: 30-200 ohm. o Short term (1 minute) Housekeeping Current Stability: 10(-4). This requires that both power supply and ion chamber resistor divider network maintain stability to this level. Signal leakage current must be stable to 15 pamp. o Sensitivity: 1. 1 Rad=0.089 uC for Helium filled PIC. 2. 1 Rad=0.89 uC for Argon filled PIC.
PROTECTION ION CHAMBER MODULE (PIC) Page 30-630.4 CAMAC COMMANDS F0.A0 Read unlatched trip status from channels 0-3. R1=Ch0.ThA, R2=Ch0.ThB, ... R16=Ch3.ThD 1=Tripped, 0=Untripped. Q=1. F0.A1 Read unlatched trip status from channel 4 and current monitor status from channels 0-4. R1=Ch4.ThA ... R4=Ch4.ThD, R5=Ch0.HiI, R6=Ch0.LoI, ... R14=Ch4.LoI 1=Tripped, 0=Untripped. Q=1. F1.A0 Read integration times for slow integrators, channels 0-4. Integration time is specified by a 2-bit field for each channel packed as: R1=Ch0LSB, R2=Ch0MSB, R3=Ch1LSB, R4=Ch1MSB, ... R10=Ch4MSB. Each 4-bit field determines one of four times as: 00=50ms, 01=100ms,10=500ms, 11=1000ms. Q=1. F1.A11 Read MIL-1553B port address R1=LSB,R5=MSB of address. Q=1. F1.A12 Read channel lock register. R1=Ch0, ... R5=Ch4. R6=GLOBAL LOCK. 1=locked, 0=unlocked. For an individual channel lock to be effective its bit in the channel lock register must be set, AND the global lock must be on. Q=1. F2.A0 Read & clear latched trip status from channels 0-3. R1=Ch0.ThA, R2=Ch0.ThB, ... R16=Ch3.ThD 1=Tripped, 0=Untripped. Q=1. F2.A1 Read & clear latched trip status from channel 4 and latched current monitor status from channels 0-4. R1=Ch4.ThA ... R4=Ch4.ThD, R5=Ch0.HI, R6=Ch0.LI, ... R14=Ch4.LI 1=Tripped, 0=Untripped. Q=1. Note that reset works independently of lock status. F2.A14 Read software trip register for channels 0-4. R1=Ch0A, R2=Ch0B,..R5=Ch1A, R6=Ch1B,...R16=Ch4D. The test current is set by DAC A, the DAC that sets threshold A, and its magnitude is set to cause the slow integrator voltage output to be 1.1 that of DAC A. Thus Comparator A should always trip under software test. Thresholds B, C, and D can be checked by appropriate adjustment of threshold A. 1=tripped, 0=untripped. Q=1 F3.A0 Read module identification register. 16 bits. Q=1. R1.. R8 = Revision Number (0=First production rev.) R9 .. R15 is the Module Type (PIC Module = 65 = 41 Hex) R16 = 1 for preproduction, = 0 for production model. Q=1. F3.A1 Read module serial number register. 16 bits. Q=1.
PROTECTION ION CHAMBER MODULE (PIC) Page 30-7 F4.A(0..4) Read fast integrator values, A0 for channel 0, ... A4 for channel 4. Q=1 if at least one trigger and subsequent digitization has occurred since the last read of same channel, otherwise Q=0. Values are 16 bit unsigned integers. F4.A(5-9) Read slow unamplified integrator values, A5 for channel 0, ... A9 for channel 4.Q=1 if at least one trigger and subsequent digitizationhas occurred since the last read of same channel, otherwise Q=0. Values are 16 bit unsigned integers. F4.A(10-14) Read slow amplified integrator values, A10 for channel 0, ... A14 for channel 4. Q=1 if at least one trigger and subsequent digitization has occurred since the last read of the same channel, otherwise Q=0. Values are 16 bit unsigned integers. F5.A0 Read threshold settings for slow integrator sequentially according to channel and threshold address registers. (See F17.A8) Threshold address is incremented after each read and rolls over to 0 after 3. Channel address register is incremented when threshold address rolls over but does not itself roll over to 0 after last channel is read. If the first read is Ch0 DAC A, the channel count will roll over after 8 channels are read, i.e. 32 reads. Q=1 for the first 20, correct, reads, and Q=0 for reads 21 to 32, which are non existent. Threshold is 12 bit unsigned integer R1=LSB,R12=MSB. F9.A0 Initialize module(CLR). This command executes only when the module is in the unlocked state. Q=1 only if module unlocked. F17.A0 Load integration times for slow integrators, channels 0-4. Integration time is specified by a 2-bit word for each channel packed as: W1=Ch0LSB, W2=Ch0MSB,... W10=Ch4MSB. Each word determines one of four times: 00=50ms, 01=100ms, 10=500ms, 11=1000ms. (The high order 6 bits are unused). The channels can be individually locked. Q=0 if any one of the five channels is locked, as a warning of possible fault. F17.A8 Load the channel address register for loading and reading the slow integrator threshold settings with F21.A0 and F5.A0. Three bits are used, W1(LSB), W2, W3, to address channels 0=Ch0, 1=Ch1,... 4=Ch4. In addition to the channel address there is internally a 2-bit register address to select which of the four thresholds to load or read. The F17.A8 command resets that 2-bit register to 0 so that the next load or read will access the first, threshold A, of four thresholds, A..D, for the selected channel. Q=1. This command is not affected by the locking mechanism. F17.A11 Load MIL-1553B port address W1=LSB,W5=MSB of address. This command executes only if the module is in the unlocked state (global lock=0). Q=1 only if module unlocked. F17.A12 Load channel lock register. W1=Ch0, ... W5=Ch4.
PROTECTION ION CHAMBER MODULE (PIC) Page 30-8 1=locked, 0=unlocked. This command executes only if the module is in the unlocked state. Q=1 only if the module is unlocked. For the individual channel locks to be effective, the global lock must be set on again, after being off to change the lock register. F18.A14 Load software test register for channels 0-3 threshold test. W1=Ch0A, W2=Ch0B,... W5=Ch1A,...W16=Ch3D. The channels can be indiviually locked. Q=0 as a warning of possibe fault if any of channels 0-3 are locked. F18A15 Load software test register for Ch4 threshold test and Ch0-Ch4 high and low current trips. W1=Ch4A, W2=Ch4B,.. W4=Ch4D, W5=Ch0HI, W6=Ch0LI, ...W14=Ch4LI. The channels can be individually locked, and if any of channels 0-4 are locked, Q=0 as a warning of possible fault. F21.A0 Load threshold settings for slow integrator sequentially according to channel and threshold address registers. (See F17.A8) Threshold address is incremented after each load and rolls over to 0 after 3. Channel address register is incremented when threshold address rolls over but does not itself roll over to 0 after last channel is loaded. Threshold is 12 bit unsigned integer W1=LSB,...W12=MSB. Q=0 if channel addressed is locked, =1 if unlocked. F29.A14 Unlock module. Q=1. F29.A15 Lock module. Q=1. X=1 is generated for all F and A combinations listed above and X=0, Q=0 for any F and A combinations not listed above.30.5 MIL-1553B INTERFACE
30.5.1 Simple Receive/Transmitter (SRT) MIL-1553B Module MIL-1553B RT Module is designed to transmit data to a Bus Controller. It does not respond to attempts to write data to it. RT address (0-30) are set via CAMAC. Limited Mode Code Commands: Mode Code Name --------- ---- 00010 (2) Xmit Last Stat Word 01000 (8) Reset 10010 (18) Xmit Last Valid Cmd Error detection by SRT is summed and reported in single Message Error bit (bit time 6). All MIL-1553B data transfers are MSB first.
PROTECTION ION CHAMBER MODULE (PIC) Page 30-9 Status Register: MSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 4 3 2 1 0 -------------------------- RT Address x ----------------------- Message Error x x x x x ------------ Invalid x ---------- Broad CMD Receive x x x x -- Invalid30.5.2 Data Format The MIL-1553B Interface of the PIC module can be read with a request for 1, 2, 3 or 4 16-bit words. The data will be arranged as follows: Word 1: B1=LSB=Ch0.ThA, B2=Ch0.ThB, ... B16=MSB=Ch3.ThD 0=Tripped, 1=Untripped. Word 2: B1=Ch4.ThA ... B4=Ch4.ThD, B5=Ch0.HiI, B6=Ch0.LoI, ... B14=Ch4.LoI 0=Tripped, 1=Untripped. Word 3: Four nibbles of hexadecimal "5" such that B1=LSB=1, B2=0, ... B16=MSB=0. Word 4: Four nibbles of hexadecimal "A" such that B1=LSB=0, B2=1, ... B16=MSB=1.
30.6 RESPONSIBLE ENGINEERS D. Hutchinson, R. Noriega