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28.1 FRONT PANEL . . . . . . . . . . . . . . . . . . 28-1
28.2 CAMAC UPPER BACKPLANE . . . . . . . . . . . . . 28-1
28.3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 28-1
28.4 OPERATIONAL DESCRIPTION . . . . . . . . . . . . 28-2
28.5 CAMAC COMMAND SUMMARY . . . . . . . . . . . . . 28-4
28.6 POWER SUPPLY REQUIREMENTS . . . . . . . . . . . 28-7
28.7 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 28-7
28.8 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 28-7 CHAPTER 28 PROGRAMMABLE DELAY UNIT II (PDUII)
28.1 FRONT PANEL o Double Width CAMAC Module o Isolated BNC connector to receive FIDO output o CAMAC "X" LED o "Fiducial Detect" LED o "Missing Fiducial" LED o "Stretched Fiducial" NIM Output on a BNC Connector
28.2 CAMAC UPPER BACKPLANE o 16 Differential ECL Channels; pulse width: 8 x 8.4 nsec =
67.2 nsec o 119 MHz with missing pulse from FIDO o -2 V @ 12 mA/CAMAC Module for terminations in other modules
28.3 FUNCTIONAL DESCRIPTION The module provides 16 independent channels of signals delayed relative to the fiducial received from the FIDO. Delays are programmable in ~8.4 nsec (1/1.19E+8 Hz) increments, and the delayed signals are pulses ~67.2 nsec (8/1.19E+8 Hz) long. Delay values for each channel are obtained at fiducial time by looking up the appropriate entry in the Pattern Timing Table. The desired values are selected by using the PP or the YY value stored in one of three PP/YY Pattern Input Registers as an index pointer into the Pattern Timing
PROGRAMMABLE DELAY UNIT II (PDUII) Page 28-2 Table, by using the modulo-36 Time Slot Counter as an index pointer into the Pattern Timing Table, or by using Pattern Timing Table location 'FF'H dedicated to reuse/standby operation. This choice is determined by the values stored in the PP/YY Mode Select Table. The delay values of interest are transferred from the Pattern Timing Table to two Semi-Custom Integrated Circuits, the Eight Channel Alarm Clock (ECAC). Once all of the 16 channels have been set up, the PP/YY Pattern Input Registers are overwritten with the standby pointer value of 0FFFFH, the Time Slot Counter is incremented, and the ouputs of the ECACs are enabled. The outputs of the ECAC drive the auxilliary upper backplane, distributing the required timing signals. Fiducial detection resets a counter in the ECAC, which is incremented by the 119 MHz clock from the FIDO. When the time elapsed since the fiducial, indicated by the count, is equal to a value stored in the ECAC, an output pulse 8 clock cycles long is generated.28.4 OPERATIONAL DESCRIPTION The Pattern Timing Table Pointer Register is written to with an F(17)A(0) W1-W12. The 8 least significant bits (W1-W8) are the PP/YY pattern pointer field. The 4 most significant bits (W9-W12) are the channel pointer field, selecting one of the 16 channels. The PP/YY Mode Select Register is written to with an F(17)A(1) W1-W4, for the channel specified by the channel pointer field of the Pattern Timing Table Pointer ( F(17)A(0) W9-W12 ). This register determines whether or not a channel is selected for reuse operation, whether the PP field or the YY field from a particular one of the three PP/YY Pattern Input Registers is to be used as a pointer into the Pattern Timing Table, or whether the contents of the modulo-36 Time Slot Counter is to be used as a pointer into the Pattern Timing Table. Mode Select bits are allocated as follows: WWWW MODE 4321 x000 YY Field of F(19)A(8) (W1-W8) x001 PP Field of F(19)A(8) (W9-W16) x010 YY Field of F(19)A(9) (W1-W8) x011 PP Field of F(19)A(9) (W9-W16) x100 YY Field of F(19)A(10) (W1-W8) x101 PP Field of F(19)A(10) (W9-W16) x110 modulo-36 Time Slot Counter x111 Reuse Operation - PP/YY pattern pointer will always equal 0FFH F(1)A(0) reads out the contents of the Pattern Timing Table Pointer register on bits R1-R12, and the Mode Select Register for the selected channel is read out on bits R13-R16. 20 bit timing delay values are written into the Pattern Timing Table with an F(16)A(0-1) and are read out with an F(0)A(0-1) at the address specified by the contents of the Pattern Timing Table Pointer
PROGRAMMABLE DELAY UNIT II (PDUII) Page 28-3 Register. Following a read or write with an A(0), the contents of the PP/YY pattern pointer field of the Pattern Timing Table Pointer Register are incremented. The Pattern Timing Table Pointer is not post incremented with an A(1). Values loaded into the Pattern Timing Table at the location specified by the PP/YY pattern pointer field equal to 'FF'H represent the timing values used for reuse/standby operation. A modulo-36 Time Slot Counter is included in the module for applications requiring Beam Pattern Independent triggers at rates as low as 10 Hz. The counter is written into with an F(19)A(11) W1-W6, indicating the time slot to be associated with the next detected fiducial. Following fiducial detection and ECAC programming, this counter is incremented. Note, for example, that if pattern independent triggering at 60 Hz is desired, it is necessary to program 6 locations in the Pattern Timing Table. The Counter will be reset when the YY (W8-W1) field of an F(19)A(8) is equal to 'F8'H through 'FF'H ('11111xxx'B). This provides an alternative scheme for the resynchroniziation of the counter. The PP/YY Pattern Input Registers are used to store the values of the pipelined beam codes, as generated by the master pattern generator (MPG). The 3 values are written to with an F(19)A(8-10). The 8 least significant bits (W1-W8) of these registers contain the YY value and the next 8 most significant bits (W9-W16) contain the PP value. After a fiducial is detected and the ECAC has been set up using pointers provided by the PP/YY Pattern Input Registers, these registers are overwritten with 0FFFFH. This insures that if no subsequent reloading of the register occurs before the next fiducial, all channels will be programmed to their standby values since the PP and YY fields of the registers will both point to the reuse/standby locations of the Pattern Timing Table. No Q or X response is returned for these commands. An F(1)A(1) R1-R8 will read out the area of the Pattern Input Register defined by the mode selected for a channel specified by the Pattern Timing Table Pointer. For example, after writing to the Pattern Timing Table Pointer with an F(17)A(0) the data '000'H, and then selecting channel 0's mode as 0 by writing a '0'H with an F(17)A(1), the data read out with an F(1)A(1) would be the data written with an F(19)A(8) W1-W8. Setting the mode to be the time slot counter by writing a '6'H with an F(17)A(1) would allow the time slot counter to be read out with an F(1)A(1). LAM generation is enabled with an F(26)A(0) and disabled with an F(24)A(0). Distribution of the output signals to the upper backplane is enabled with an F(26)A(1) and disabled with an F(24)A(1). The logic sequencer which loads the ECAC's after fiducial detection is enabled with an F(26)A(2), and disabled with an F(24)A(2). It is possible to run the module off of an internal 8 MHz clock for diagnostic operations without a FIDO providing the standard 119 MHz clock with missing pulse. An F(26)A(3) enables operation with the 8
PROGRAMMABLE DELAY UNIT II (PDUII) Page 28-4 MHz clock, an F(24)A(3) disables the internal clock, making the module dependent upon the external clock input. A fiducial will be generated internally with an F(27)A(0), for use with the local 8 MHz clock or for running with external clock inputs not generating the 119 MHz missing pulse fiducial. An F(2)A(2) will read out a status register. Status bits are defined as follows: R1 - LAM Enabled R2 - Output Enabled R3 - Sequencer Enabled R4 - Local 8 MHz clock selected R5 - undefined R6 - undefined R7 - Fiducial Detected (reset after readout) R8 - Fiducial Missing (reset after readout) If a fiducial is not detected within '80000'H (approximately 4.4 msec at 119 MHz) or '100000'H (approximately 8.8 msec at 119 MHz) clock cycles, as determined by a jumper, the Fiducial Missing bit will be set, the front panel Fiducial Missing LED will be lit, and a LAM will be generated if enabled by an F(26)A(0). An F(2)A(2) or an F(10)A(0) will reset this bit (along with the Fiducial Detected status bit). The Q response to an F(8)A(0) will reflect the state of this Missing Fiducial status bit. Detection of a Fiducial wil set the Fiducial Detected bit, and light the front panel Fiducial Detect LED for approximately 3 msec. The module is reset with an F(9)A(0), or a Z*S2. This results in all F(26)/F(24) features being disabled, and all entries in the Pattern Timing Table set to 0FFFFFH. An X = 1 response is generated for each of the above commands, unless otherwise noted. Q = 1 response is generated for the above commands (unless otherwise noted) if the module is not busy doing other things, such as loading the ECAC (for ~12 usec following fiducial detection with the sequencer enabled), or initializing the Pattern Timing Table (for ~1 msec following a module reset command).28.5 CAMAC COMMAND SUMMARY o F(17)A(0) W12-W9 sets the channel field of the Pattern Timing Table Pointer (PTTP), W8-W1 sets the PP/YY field of the PTTP
PROGRAMMABLE DELAY UNIT II (PDUII) Page 28-5 o F(17)A(1) W4-W1 sets the PP/YY mode for the channel selected by the PTTP, as listed below: WWWW MODE 4321 x000 YY Field of F(19)A(8) (W1-W8) x001 PP Field of F(19)A(8) (W9-W16) x010 YY Field of F(19)A(9) (W1-W8) x011 PP Field of F(19)A(9) (W9-W16) x100 YY Field of F(19)A(10) (W1-W8) x101 PP Field of F(19)A(10) (W9-W16) x110 modulo-36 Time Slot Counter x111 Reuse Operation - PP/YY pattern pointer will always equal 0FFH o F(1)A(0) R16-R13 reads back the PP/YY mode associated with the channel selected by the PTTP, R12-R1 reads back the PTTP o F(16)A(0) W24-W1 are written into the Pattern Timing Table (PTT) at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is incremented following this operation. o F(16)A(1) W24-W1 are written into the Pattern Timing Table (PTT) at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is not incremented following this operation. o F(0)A(0) R24-R1 read out the PTT at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is incremented following this operation. o F(0)A(1) R24-R1 read out the PTT at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is not incremented following this operation. o F(19)A(8-10) W16-W1 write the pipelined PP/YY pattern registers. The modulo-36 time slot counter is reset with an F(19)A(8) W8-W4 = '11111'B. o F(19)A(11) W8-W1 sets the modulo-36 time slot counter. This counter is incremented following the detection of a fiducial, and denotes the time slot to be associated with the next fiducial. o F(1)A(1) R8-R1 reads out the pipelined PP/YY pattern register selected by the mode associated with the channel defined in the PTTP.
PROGRAMMABLE DELAY UNIT II (PDUII) Page 28-6 o F(26)A(0) enables LAM generation by a missing fiducial o F(24)A(0) disables LAM generation by a missing fiducial o F(26)A(1) enables distribution of timing pulses on the upper backplane o F(24)A(1) disables distribution of timing pulses on the upper backplane o F(26)A(2) enables the sequencer inside the PDUII, allowing it to respond to detected fiducials o F(24)A(2) disables the sequencer inside the PDUII o F(26)A(3) enables a local 8MHz clock as the delay generating reference o F(24)A(3) disables the local 8MHz clock. The external 119MHz clock (from the FIDO) is used as the delay generating reference. o F(2)A(2) R8-R1 reads out a status register as follows: R1 - LAM Enabled R2 - Output Enabled R3 - Sequencer Enabled R4 - Local 8 MHz clock selected R5 - undefined R6 - undefined R7 - Fiducial Detected (reset after readout) R8 - Fiducial Missing (reset after readout) o F(8)A(0) Q=0 indicates no missing fiducials have been detected, Q=1 indicates a missing fiducial has been detected. This command tests the LAM source. o F(10)A(0) resets the missing fiducial and fiducial detected latches. (Clears the LAM source) o F(27)A(0) locallly generates a fiducial. For diagnostic purposes with the local 8MHz clock. o F(9)A(0) resets the module, disables all F(24/26) features, and initializes all PTT locations to 'FFFFFF'H. o Z*S2 resets the module, disables all F(24/26) features, and initializes all PTT locations to 'FFFFFF'H.
PROGRAMMABLE DELAY UNIT II (PDUII) Page 28-728.6 POWER SUPPLY REQUIREMENTS +6V @ 1.5A -6V @ 2.0A Y1 (aux -6V supply) @ 3.0A
28.7 DRAWING PACKAGE NUMBER 233-002
28.8 RESPONSIBLE ENGINEER E. Linstadt