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25.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . 25-1

25.1.1 Single Width CAMAC Module . . . . . . . . . . 25-1

25.1.2 Front Panel . . . . . . . . . . . . . . . . . 25-1

25.1.3 Module Reset . . . . . . . . . . . . . . . . . 25-1

25.2 OUTPUT CONTROL . . . . . . . . . . . . . . . . . 25-2

25.2.1 Output Value (DAC channel) Selection . . . . . 25-2

25.2.2 Typical Output Timing (PDU Channel 0 Operation) 25-3

25.3 ANALOG INPUT . . . . . . . . . . . . . . . . . . 25-4

25.3.1 IEEE Format . . . . . . . . . . . . . . . . . 25-4

25.3.2 VAX/VMS Format . . . . . . . . . . . . . . . . 25-5

25.4 OPTIONS CONTROL REGISTER . . . . . . . . . . . . 25-5

25.4.1 Remote Device Status . . . . . . . . . . . . . 25-5

25.5 REMOTE DEVICE CONTROL . . . . . . . . . . . . . 25-6

25.6 Q AND X RESPONSE . . . . . . . . . . . . . . . . 25-6

25.7 POWER-ON CONSIDERATIONS . . . . . . . . . . . . 25-6

25.7.1 F-Code SUMMARY . . . . . . . . . . . . . . . . 25-7

25.8 POWER SUPPLY REQUIREMENTS . . . . . . . . . . . 25-7

25.9 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 25-8

25.10 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . 25-8

25.11 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 25-8 CHAPTER 25 PULSED AMPLITUDE UNIT (PAU) The Pulsed Amplitude Unit (PAU) provides pattern dependent output voltages on a beam-by-beam basis, for controlling devices such as magnets and phase shifters. Up to 32 different values of output voltage (DAC outputs or DAC channels) are available from the single analog output of the module. Any of these values may be associated with (mapped to) any of the 256 allowed Pulse Codes (PP). The DAC output values and the mapping of PP values to DAC output values are determined by memory within the module which is loaded before the PP are sent. An ADC is provided which digitizes an analog input signal at the appropriate beam time and stores it in a buffer memory within the module. This input is normally used to monitor the controlled device response at each beam. To minimize software modification, the PAU is as nearly software compatible with the Transiac 3016 DAC and the Smart Analog Module (SAM) as possible, within practical design constraints.


25.1.1 Single Width CAMAC Module

25.1.2 Front Panel 36-pin AMP connector (AMP Part No. 204731-2) for device interconnect. LED indicates X-response. Pin assignments for this connector are listed below.

25.1.3 Module Reset F9 A0, Z*S2, or power-on clears the module. See below for power-on considerations.


25.2 OUTPUT CONTROL The output of the PAU is controlled by the receipt of the broadcast beam code (PPYY) indicating the DAC output value (logical DAC output channel) to be used. The choice of the DAC output value associated with a specific beam is contained in the Pulse Code Mapping Table (PCMT). Each beam (PP) has an entry in the table which points either at a specific DAC channel, or, in the special case of pipelined operation, is loaded with a special Do Nothing value. Each DAC output value (logical DAC channel) may be associated with any number of beams. Channel 0 is by convention the channel associated with null and deactivated beams.

25.2.1 Output Value (DAC channel) Selection DAC Control - The programming of the 32 logical DAC output channels is accomplished with F16 A(n) and F21 A(n) Function Codes for the first and second block of 16 DAC channels respectively. The programmed values are read with F0 A(n) and F5 A(n). respectively. Programming of the outputs is with 16 bit left justified offset binary numbers. The low order nibble is not used, and reads back as 0. CAMAC Data DAC Output ---------- ---------- '000x'X -10.00 Volts '800x'X 0.00 Volts 'FFFx'X +10.00 Volts The association of PP codes with DAC output values is determined by the Pulse Code Mapping Table (PCMT) which assigns one of the 32 DAC output values (logical channels 0 through 31) to each of the 256 possible Beam Codes (PP's). Pulse Code Mapping Table Pointer - The Pulse Code Mapping Table (PCMT) is accessed through CAMAC with the PCMT Pointer Register which is programmed with an F17 A1 command to point to the desired table element. Reading or writing a PCMT table element increments this register. Pulse Code Mapping Table - The PCMT is 256 elements long and is mapped one-to-one to the Beam Codes (PP) broadcast on bits W9 through W16 of the selected F19 A(k) function code. The PCMT is loaded with the logical DAC channel number (0-31) associated with each beam. An exception is the logical channel 32 which is the Do Nothing channel and is used to inhibit the loading of the output DAC with a new value. This is required when the PAU is used in it's Pipelined mode.

PULSED AMPLITUDE UNIT (PAU) Page 25-3 Reading and writing of the PCMT is accomplished with the PCMT Register (above) and by CAMAC functions F1 A1 and F17 A1 respectively. Reading or writing increments the PCMT pointer register. Timing - The next DAC value for output is selected by the most recent valid PP Code, which is received in bits W9 through W16 of F19 A(k), where k may be 8,9 or 10. The sub-address to which the module responds, A(k), is selected by bits W4 and W5 in the Options Control Register. Usually, the PAU timing is determined by Channel 0 of the Programmable Delay Unit (PDU). This is nominally beam time. The PP code for setting the DAC output may not be received until after the current beam passes. Therefore the module receives the PP code for the DAC setting required at the next beam. The DAC changes state 1000 +/- 100 microseconds after beam time, (beam time is defined by PDU output 0). The F19 A(k) for setting the DAC must be received before this time. Additionally, the PAU times-out and disables the analog output if the Beam Codes F19 A(k) and PDU output have not been received within the last 10 mS. PAU timing may alternately be derived from PDU Channel 13, by setting W6 in the Options Control Register. The DAC then changes state 1000 +/- 100 microseconds after receipt of PDU Channel 13, and the ADC digitizes at the same time as PDU Channel 13 (at the next beam time). Output - The DAC output to the controlled device is +/-10 volts with a 20 Ohm source impedance. 10 Ohms is provided in series with both the output and the return lines. Initial output accuracy is 0.1% of full-scale at 25 degrees Celsius, with drift of less than 0.1% of full-scale at any temperature from 0 to 50 degrees Celsius.

25.2.2 Typical Output Timing (PDU Channel 0 Operation) The PAU must control some devices which require more than one beam period to reach stable operation, and special consideration must be given to the characteristics of these devices when programming the PAU. Sub-address A8 is reserved for devices that can respond within one beam period, A9 for devices that require two beam periods, and A10 for devices needing three beam periods. Note that a PP instructing the PAU to do nothing (F19 A(k) with bit W6 set) must be sent to the PAU while the controlled device is changing state. Sub-Address Time (t) available Comments for controlled device to stabilize ------------- --------------------- ---------------------------- A8 1.78 mS Controlled device can change state at next beam.

PULSED AMPLITUDE UNIT (PAU) Page 25-4 A9 4.56 mS Controlled device requires two beam periods to stabilize. One Do Nothing PP required. A10 7.33 mS Controlled device requires three beam periods to stabilize. Two "do nothing" PPs required. Normally, the F19 A(k) command to the PAU will be received within +/- 1000 microseconds of the current beam. A timing chart is included in the drawing package for this module, showing operation from Channel 0 of the PDU with normal beam timing.

25.3 ANALOG INPUT An Analog/Digital Converter (ADC) measures the response of the controlled device at each appropriate beam time and saves it in a buffer memory. The PAU has a sample/hold which starts tracking the analog signal when the DAC changes state. It stops tracking, holds and digitizes the input at the appropriate beam time for stable device response, as determined by the appropriate (Channel 0 or Channel 13) output from the PDU, and by the F19 A(k) which initiated the DAC output. Therefore, the buffer memory contains the device response to each output channel of the DAC at the last time that channel produced stable output. An error flag identifies ADC data that is not up-to-date. This is data which is read after the corresponding DAC value (channel) has been changed, but not yet used for output and read by the ADC. This flag is set when the DAC channel is set, and cleared when the ADC completes digitizing the new value. The error flag is also set if the analog output is disabled during an ADC conversion. The 12-bit ADC reading is placed in a buffer memory and converted to a real*4 floating point number when read. Format is compatible with IEEE or VAX format as determined by the options control register and is as below:

25.3.1 IEEE Format 1. First CAMAC Read -- Low order word of floating point result (least significant part of mantissa). The least significant bit (Bit 0 -- CAMAC R1) contains the Error Bit. 2. Second CAMAC Read -- High order word of floating point result (sign, exponent, and mantissa).


25.3.2 VAX/VMS Format 1. First CAMAC Read -- High order word of floating point result (sign, exponent, and mantissa). 2. Second CAMAC Read -- Low order word of floating point result (least significant part of mantissa). The least significant bit (Bit 0 -- CAMAC R1) contains the Error Bit. The ADC buffer memory is read using F1 A0 for each read. The starting output (channel) is set by the ADC Pointer Register with W1 thru W5 containing the channel number. The ADC Pointer Register is set by F(18) A(0) and read by F(2) A(0). Numbers are read sequentially with two 16-bit reads per number. Analog input is bi-polar. Sensitivity is +/-10 volts full-scale. The input is a high-impedance differential instrumentation amplifier with 1K resistors in series with each input lead for input protection. Maximum input voltage is +/-30 volts. Initial gain error is less than

0.1% of full-scale at 25 degrees Celsius. Drift is less than 0.1% of full-scale from 0 to 50 degrees Celsius.

25.4 OPTIONS CONTROL REGISTER This register is loaded by F17 A1. Bit assignments are as follows: Bits Function ------ --------------------------------------------------- W1, W2 Not used. (Provided for program compatability with the Smart Analog Module (SAM). W3 0 = VAX Floating point format 1 = IEEE Floating point format. (Default following module clear.) W4, W5 Determine sub-address for F19 as follows: W5 W4 Sub-address 0 0 A8 (Default following Clear) 0 1 A9 1 0 A10 W6 0 = PAU timing from PDU Channel 0 1 = PAU timing from PDU Channel 1

25.4.1 Remote Device Status Up to four status bits can be received from the controlled device through optically coupled receivers. These bits are read by F2 A0.

PULSED AMPLITUDE UNIT (PAU) Page 25-6 Logical 1 is defined as a signal between +3 and +30 volts. Logical 0 is defined as a signal between -30 and +1 volts. See section on front-panel connector for pin assignments.

25.5 REMOTE DEVICE CONTROL Up to four control bits can be sent to the controlled device through optically coupled drivers. These bits are written by F20 A1. All four bits are cleared by F9 A0, Z*S2, or power-on. The output is a logical 1 if the output driver is turned on (saturated transistor). Output driver saturation voltage is 1 volt maximum at 100 mA. Collector to emitter breakdown is 80 volts minimum, and dark current is less than 100 uA at 80 volts. See section on front-panel connector for pin assignments.

25.6 Q AND X RESPONSE The PAU responds with Q and X as follows: o Q=1 response is produced on receipt of all F-Codes to which the module responds, except F(19). Q=0 is produced if the module is busy with internal functions such as writing to the ADC memory at the same time an effort is made to read the ADC. Q=0 for all f(19) commands. o X=1 is produced on receipt of all F-Codes to which the module responds except f(19).

25.7 POWER-ON CONSIDERATIONS The following are unspecified when the module is initially powered, and must be written to the module: o The DAC settings associated with the selected PP. o The PP recognized by the module (the PP Mapping Table) and the PP Mapping Table Pointer Register setting. o The ADC Pointer Register setting.

PULSED AMPLITUDE UNIT (PAU) Page 25-7 The analog output from the module is initially disabled and at zero volts output. After the above initialization is performed with software, the output may be enabled by F26 A0. The output may be disabled, at any time, with an F24 A0. This feature of the module may be tested with F(27) A(0). Q=1 if the analog output is enabled, and Q=0 if it is disabled.

25.7.1 F-Code SUMMARY F-Code/Sub-address Function F0 A(N) Reads 1st 16 DAC settings. F1 A0 Read ADC Buffer Memory. F1 A1 Read PP mapping Table Register Pointer. F2 A0 Read ADC Pointer Register. F2 A1 Read Remote Device Status. F4 A0 Read PP Mapping Table. F5 A(N) Reads 2nd 16 DAC settings. F9 A0 Clears the module. F16 A(N) Writes 16 DAC output values. F17 A0 Write Options Control Register. F17 A1 Write PP Maping Table Reg Pointer. F18 A0 Write ADC Pointer Register. F19 A8 Used by PAU for devices. that require 1 beam period for stability. F19 A9 Used by PAU for devices. that require 2 beam periods for stability. F19 A10 Used by PAU for devices. that require 3 beam periods for stability. F20 A0 Write PP Mapping Table. F20 A1 Write Remote Device Control Bits. F21 A(N) Write 2nd group of DAC outputs. F24 A0 Disables PAU Analog Output. F26 A0 Enables PAU Analog Output. F27 A0 Test Analog Output Enable. (Q=1 for enabled).

25.8 POWER SUPPLY REQUIREMENTS o +6 volts at 3.0 amps o +24 volts at 100 ma o -24 volts at 100 ma



25.10 PIN ASSIGNMENTS Pin assignments for these signals on the front panel connector are as follows: Bit CAMAC Source Return Signal 0 R1 B1 B2 Input 0 1 R2 B3 B4 Input 1 2 R3 B5 B6 Input 2 3 R4 B7 B8 Input 3 0 W1 A1 A2 Output 0 1 W2 A3 A4 Output 1 2 W3 A5 A6 Output 2 3 W4 A7 A8 Output 3 -- ----- A11 A12 Analog Output -- ----- A9 -- Analog Input (+) -- ----- A10 -- Analog Input (-) -- ----- -- C10 ground -- ----- -- C11 ground -- ----- -- C12 ground


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Contact (until Aug. 15, 1996): Jeffrey Miller
Owner: Bob Sass

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