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24.1 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 24-1
24.2 PROGRAMMING CONSIDERATIONS . . . . . . . . . . . 24-1
24.3 MEMORY MAPPING . . . . . . . . . . . . . . . . . 24-2
24.4 ID REGISTER . . . . . . . . . . . . . . . . . . 24-2
24.5 TYPE REGISTER . . . . . . . . . . . . . . . . . 24-2
24.6 COMMAND REGISTER . . . . . . . . . . . . . . . . 24-3
24.7 STATUS REGISTER . . . . . . . . . . . . . . . . 24-4
24.8 PHASE SHIFT DAC . . . . . . . . . . . . . . . . 24-5
24.9 CLOCK CONTROL DIVISOR . . . . . . . . . . . . . 24-5
24.10 WOBBLE CONTROL DIVISOR . . . . . . . . . . . . . 24-5
24.11 SPECIAL RESET LOCATION . . . . . . . . . . . . . 24-5
24.12 ADC DATA BLOCK STRUCTURE . . . . . . . . . . . . 24-5
24.13 REFERENCES . . . . . . . . . . . . . . . . . . . 24-6
24.14 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 24-6
24.15 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 24-6 CHAPTER 24 PHASE AND AMPLITUDE DETECTOR (PAD) This chapter describes the operation of the PAD and the manner of its interaction with the PIOP. This note does not address the principles of the measurement tech- niques or the details of the electronic circuitry. The technically- minded are referred to references #1 and #2.
24.1 FUNCTIONAL DESCRIPTION The phase and amplitude head contains microwave circuitry, analog circuitry, A/D and D/A circuitry, and a programmable digital system which controls these components. The digital system in the phase head utilizes two programmable logic sequencers to operate and control the digital circuity of analog multiplexer and analog-to-digital converter components, while the other logic sequencer is used to control the interface to the PIOP's external multiplexed bus. These two sequencers are transparent to the 8088 code in the PIOP, and all operations are controlled through memory mapped control, status, and parameter registers.
24.2 PROGRAMMING CONSIDERATIONS The phase and amplitude head is interfaced to the PIOP system via a 256 byte memory-mapped control block. This control block provides control and status functions and serves as a data buffer for the measurement functions of the head. Each head utilizes 128 bytes of the memory-mapped address space, allowing two heads to be daisy chained together on one PIOP cable. A programmable jumper on the digital electronics board (labeled "SO" on the schematic) specifies which of the two possible address blocks the unit is mapped into. Table #1 details the memory mapping. ______________________________ This chapter is adapted from a memo by J. D. Fox dated 6/2/83 and titled "Phase and Amplitude Head PIOP Interface, Version 1.2."
PHASE AND AMPLITUDE DETECTOR (PAD) Page 24-224.3 MEMORY MAPPING Relative Address (*) Function Comment 0 Type No. read only 1 ID No. read only 2 command register 3 status register read only 4 phase shift DAC 5 clock control divisor 6 wobble control divisor 7-A available memory 10-1F ADC data block 20-2F available memory 30-3F offset ADC data block 40-7F available memory FF (**) special reset location R or W causes hardware reset (*) Absolute address = '80'Hex*S1 + '4000'Hex relative address (**) Absolute address = '40FF'Hex All locations (except the three marked read only) can be treated as available 8088 memory, albeit with an access time penalty due to the PIOP interface. A brief description of each of these registers follows.
24.4 ID REGISTER An eight bit read-only switch register which contains the unit's serial number.
24.5 TYPE REGISTER An eight bit read-only switch register which reflects the type and revision level of the system. Two types are implemented: TYPE "FF" -- Revision 1 system TYPE "FE" -- Revision 2 system
PHASE AND AMPLITUDE DETECTOR (PAD) Page 24-324.6 COMMAND REGISTER The command register is an eight-bit R/W register which controls the operation of the digital system. It is structured as follows: o bit 0 Set +pi/2 wobbler (negative true). o bit 1 Set -pi/2 wobbler (negative true). o bit 2 Spare (Version #1)/ Droop Digitize command (Version #2) o bit 3 ADC data block offset. o bit 4 Head interrupt enable. o bit 5 Red LED indicator (negative true). o bit 6 Green LED indicator (negative true). o bit 7 Asynchronous head digitize command. Bits 0 and 1 allow the programmer to override the wobbler logic and force the wobbler to a particular state. If both bits 0 and 1 are high, the board logic automatically modulates the wobbler at the rate specified by the wobbler divisor register. If both bits 0 and 1 are low, the wobbler will be in an undefined state. Bit 2 - Spare for future use (Version 1) Bit 3 allows the programmer to specify which of the two possible For Version #2 systems, the Droop Digitize Command is implemented via bit 2 (previously "spare") of the command register. This command starts a digitization cycle without updating the sample and hold circuits and this feature allows droop testing of the sample and hold circuits. If bit 2 is written low, then high; the low to high signal transitio will initiate the digitization cycle. Please note that bit 2 must be set high for normal system operation, and that the initialized state of this bit is a zero. Thus the power-up initialization code in the PIOP must set this bit high for proper operation. This "Digitize" command (Bit 7) of the command register functions independently, as described below> Bit 3 allows the programmer to specify which of the two possible locations the head system will place the ADC block in. This feature allows the suer to automatically keep data from the previous linac pulse available for computation without having to copy the data to a temporary buffer. Bit 4 provides control of the HEAD interrupt to the PIOP. If bit 4 is reset to zero, the head interrupt signal is reset to zero and no further head interrupts are enabled. If bit 4 is set to 1, upon completion of the next digitization cycle the head interrupt is set. Note that the head interrupt is held until reset to zero via bit 4, and if future interrupts are desired, they must be re-enabled during
PHASE AND AMPLITUDE DETECTOR (PAD) Page 24-4 each interrupt service routine. Bits 5 and 6 allow program control of the LED indicator on the front panel. Bit 7 allows the programmer to asynchronously start the digitization logic. If this bit is in the zero state, the system automatically takes data each linac pulse at the time specified by the value in the clock divisor register. If this bit is set to 1, then reset to zero, a digitization cycle is initiated in the head. This asynchronous digitization cycle operates the track and hold gates and the ADC logic, and is provided to allow the programmer to measure the offset voltage of the amplitude detector by triggering the ADC logic after a klystron pulse has occurred. Please note that both the front panel gate output and the wobbler divisor logic are affected by these operations, and the programmer should be aware that use of the asynchronous digitize feature may confuse remote oscilloscope viewers. Setting bit 7 to a 1 state places the track and hold circuit in the track state, and this mode is useful for laboratory testing of the front end amplifier and tracking amplifier circuits.24.7 STATUS REGISTER The status register is an 8-bit read only register structured as follows: o bits 0-5 future use (Version #1) Version #2 systems define the following additional bits: o bit 0 - This bit is high if the +6 supply voltage is greater than 35% of the +15 volt supply (i.e., if +6 is greater than ~5.25 volts). bit 1 - This bit is high if -6 volts is more negative than 35% of the -15 volt supply. o - Bit 2 - This bit is set if the wobbler output control voltage is greater than ~8.75 volts. o bit 3 - This bit is set if the wobbler output control voltage is more negative than ~-8.75 volts. Both versions #1 and #2 define Bits 6 and 7 as follows: o bit 6 wobble state o bit 7 fresh update The wobble state bit (bit 6) represents the state of the phase wobbler at the time the ADC data was taken. A zero represents the -pi/2 state, and a 1 represents the +pi/2 state. The fresh update bit (bit 7) is set by the completion of an ADC data digitization cycle, and is reset by a read from the status register.
PHASE AND AMPLITUDE DETECTOR (PAD) Page 24-524.8 PHASE SHIFT DAC The DAC register is a R/W 8-bit register which reflects the setting of the phase shifter control DAC. It is coded in straight binary, and the range of the DAC is 0-9.96 volts (00 corresponds to 0 volts, FF corresponds to 9.96 volts).
24.9 CLOCK CONTROL DIVISOR The clock control divisor is an eight bit R/W register which contains the number of 14.875 MHz clock cycles between the modulator-trigger pulse from the PIOP, and the actual time of data sampling in the phase and amplitude head. Each count corresponds to one 66 nanosecond period, and the register is encoded in straight binary.
24.10 WOBBLE CONTROL DIVISOR The wobble divisor register is an 8-bit R/W location which contains the divisor for the automatic phase wobbler. Each count corresponds to one linac pulse (i.e., a value of 03 would flip the phase modulator's state every third pulse). A peculiar feature of this system is that the modulator is flipped a few hundred nanoseconds after the data is taken, which can confuse remote viewers on an oscilloscope. Because of this, a value of '00' wobbles the phase every pulse (as would a value of '01') but does not flip the wobbler until several microseconds after the end of the klystron pulse.
24.11 SPECIAL RESET LOCATION The special reset function is mapped into absolute address FF (255). Reading or writing this location causes an electrical reset of the digital circuitry of the phase and amplitude head. Resetting the PAD does NOT result in a command acknowledge to the PIOP.
24.12 ADC DATA BLOCK STRUCTURE The ADC data block contains the digitized values of the eight voltages measured each digitization cycle. It is structured as eight words, with each 12-bit value left-justified in the 16-bit field. The values are coded in an offset binary format, with '0000'Hex representing -5 volts, and 'FFF0'Hex representing +5 volts. The individual words are: o WORD 0: Digitized system analog ground.
PHASE AND AMPLITUDE DETECTOR (PAD) Page 24-6 o WORD 1: Digitized phase voltage as sampled by the phase electronics. o WORD 2: Digitized amplitude voltage as sampled by the amplitude electronics, and -5 volt offset has been applied so that -5 volts corresponds to approximately zero volts from the amplitude detector. o WORD 3: Digitized temperature voltage as measured in the ambient air of the phase and amplitude head. The system has a temperature coefficient of 10 milliVolts/degrees K. o WORD 4: Digitized DAC measurement prescaled by a factor of two. The 0-10 Volt DAC is scaled to 0-5 Volts by a resistive divider. o WORD 5: Digitized +15 Volts, as multiplied by a factor of0.25 (i.e., +15 volts is scaled to 3.75 Volts). o WORD 6: Digitized -15 Volts, as multiplied by a factor of
0.25 (i.e., -15 Volts is scaled to -3.75 volts). o WORD 7: Digitized +6 and -6 supplies, the difference between +6 and -6 is scaled by 0.537 (i.e., voltages of +6 and -6 are scaled to 0.446 Volts).
24.13 REFERENCES 1. "A Microprocessor Controlled Phase Detection System for 2856 MHz Pulses," J. D. Fox and H. Schwarz, SLAC PUB 2902. 2. "Phase and Amplitude Detection System for the Stanford Linear Accelerator," J. D. Fox and H. Schwarz, SLAC PUB 3071.
24.14 DRAWING PACKAGE NUMBER 123-625
24.15 RESPONSIBLE ENGINEER J. D. Fox / M. Browne