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11.1 FRONT PANEL . . . . . . . . . . . . . . . . . . 11-1

11.2 CAMAC UPPER BACKPLANE . . . . . . . . . . . . . 11-1

11.3 THE DRTC AS A MODIFIED PDUII . . . . . . . . . . 11-1

11.4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 11-2

11.5 OPERATIONAL DESCRIPTION . . . . . . . . . . . . 11-2

11.6 CAMAC COMMAND SUMMARY . . . . . . . . . . . . . 11-2

11.7 POWER SUPPLY REQUIREMENTS . . . . . . . . . . . 11-5

11.8 DRAWING PACKAGE NUMBER . . . . . . . . . . . . . 11-5

11.9 RESPONSIBLE ENGINEER . . . . . . . . . . . . . . 11-5 CHAPTER 11 DAMPING RING TURN COUNTER (DRTC)

11.1 FRONT PANEL o Double Width CAMAC Module o BNC connector to receive ECL resynchronized 8.5 MHz output from the MTG's PEP/SPEAR module o BNC connector to receive NIM reset (NOT CAMAC reset) STBII output o CAMAC "X" LED o "Reset Detect" LED o "Missing Reset" LED o Secondary trigger (Channel 0) NIM Output on a LEMO Connector o Tertiary trigger (Channel 1) NIM Output on a LEMO Connector

11.2 CAMAC UPPER BACKPLANE o Not connected to the auxilliary upper backplane

11.3 THE DRTC AS A MODIFIED PDUII The DRTC is a specially modified PDUII module for use with the Master Trigger Generator (MTG). In most respects, the DRTC functions in a manner identical, or analogous, to that of the PDUII. The modifications made are these:


DAMPING RING TURN COUNTER (DRTC) Page 11-2 o Instead of 16 independent channels with CAMAC upper backplane outputs (numbered 0-15), there are 2 NIM on LEMO front panel outputs (numbered 0,1). These 2 channels were PDU channels 0 and 1. o The PDUII clocks on a continuous 119 MHz with missing pulse fiducial from the FIDO, the missing pulse fiducial starts the delay countdown by resetting the internal 20-bit counter. The DRTC's internal 20-bit counter is reset by the external NIM Reset from an STBII output. The delay counter is incremented by the 8.5 MHz clock recieved from the MTG's PEP/SPEAR module. (IMPORTANT: The Reset from the STBII is NOT a CAMAC reset ( F(9)A(0) ). To distinguish the two, CAMAC resets are called CAMAC resets, while the other sort are simply called resets.)

11.4 FUNCTIONAL DESCRIPTION The functioning of the DRTC is identical to that of the PDUII, except for the modifications listed in the section "The DRTC as a modified PDUII." For a functional description of the DRTC, see the Functional Description section of the PDUII chapter. The only non-trivial changes from that section are that DRTC delays are programmable in ~117.6 nsec (1/8.5E+6 Hz) increments, and the delayed signals are pulses ~941.2 nsec (8/8.5E+6 Hz) long.

11.5 OPERATIONAL DESCRIPTION The operation of the DRTC is identical to that of the PDUII, except for the modifications listed in the section "The DRTC as a modified PDUII." For an operational description of the DRTC, see the Operational Description section of the PDUII chapter. The only non-trivial changes from that section are that if the DRTC does not detect a reset from the STB within '80000'H (approximately 61.6 msec at 8.5 MHz) or '100000'H (approximately 123.2 msec at 8.5 MHz) clock cycles, as determined by a jumper, the Reset Missing bit will be set, the front panel Reset Missing LED will be lit, and a LAM will be generated if enabled by an F(26)A(0).

11.6 CAMAC COMMAND SUMMARY o F(17)A(0) W12-W9 sets the channel field of the Pattern Timing Table Pointer (PTTP), W8-W1 sets the PP/YY field of the PTTP


DAMPING RING TURN COUNTER (DRTC) Page 11-3 o F(17)A(1) W4-W1 sets the PP/YY mode for the channel selected by the PTTP, as listed below: WWWW MODE 4321 x000 YY Field of F(19)A(8) (W1-W8) x001 PP Field of F(19)A(8) (W9-W16) x010 YY Field of F(19)A(9) (W1-W8) x011 PP Field of F(19)A(9) (W9-W16) x100 YY Field of F(19)A(10) (W1-W8) x101 PP Field of F(19)A(10) (W9-W16) x110 modulo-36 Time Slot Counter x111 Reuse Operation - PP/YY pattern pointer will always equal 0FFH o F(1)A(0) R16-R13 reads back the PP/YY mode associated with the channel selected by the PTTP, R12-R1 reads back the PTTP o F(16)A(0) W24-W1 are written into the Pattern Timing Table (PTT) at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is incremented following this operation. o F(16)A(1) W24-W1 are written into the Pattern Timing Table (PTT) at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is not incremented following this operation. o F(0)A(0) R24-R1 read out the PTT at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is incremented following this operation. o F(0)A(1) R24-R1 read out the PTT at the address specified by the PTTP. Only the 20 least significant bits are used for the delay time. The PP/YY field of the PTTP is not incremented following this operation. o F(19)A(8-10) W16-W1 write the pipelined PP/YY pattern registers. The modulo-36 time slot counter is reset with an F(19)A(8) W8-W4 = '11111'B. o F(19)A(11) W8-W1 sets the modulo-36 time slot counter. This counter is incremented following the detection of a reset, and denotes the time slot to be associated with the next reset. o F(1)A(1) R8-R1 reads out the pipelined PP/YY pattern register selected by the mode associated with the channel defined in the PTTP.
DAMPING RING TURN COUNTER (DRTC) Page 11-4 o F(26)A(0) enables LAM generation by a missing reset o F(24)A(0) disables LAM generation by a missing reset o F(26)A(1) enables distribution of timing pulses on the front panel o F(24)A(1) disables distribution of timing pulses on the upper backplane o F(26)A(2) enables the sequencer inside the DRTC, allowing it to respond to detected resets o F(24)A(2) disables the sequencer inside the DRTC o F(26)A(3) enables a local 8MHz clock as the delay generating reference. o F(24)A(3) disables the local 8MHz clock. The external 8.5 MHz clock (from the MTG)is used as the delay generating reference. o F(2)A(2) R8-R1 reads out a status register as follows: R1 - LAM Enabled R2 - Output Enabled R3 - Sequencer Enabled R4 - Local 8 MHz clock selected R5 - undefined R6 - undefined R7 - Reset Detected (reset after readout) R8 - Reset Missing (reset after readout) o F(8)A(0) Q=0 indicates no missing resets have been detected, Q=1 indicates a missing reset has been detected. This command tests the LAM source. o F(10)A(0) resets the missing reset and reset detected latches. (Clears the LAM source) o F(27)A(0) locallly generates a reset. For diagnostic purposes with the local 8MHz clock. o F(9)A(0) CAMAC resets the module, disables all F(24/26) features, and initializes all PTT locations to 'FFFFFF'H. o Z*S2 CAMAC resets the module, disables all F(24/26) features, and initializes all PTT locations to 'FFFFFF'H.
DAMPING RING TURN COUNTER (DRTC) Page 11-5

11.7 POWER SUPPLY REQUIREMENTS +6V @ 1.5A -6V @ 2.0A Y1 (aux -6V supply) @ 3.0A

11.8 DRAWING PACKAGE NUMBER

11.9 RESPONSIBLE ENGINEER E. Linstadt


 
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Owner: Bob Sass

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