Meeting Agenda

17 Feb 2004

In attendance:  J. Nelson (notetaker), R. Chestnut, J. Frisch, R. Hall, J. Rock, S. Smith



Elog from unix prompt?
This works wonderfully.  Thank you!


Slow archiver? 
Is now ~2xs faster.  Bob will continue to work with Ian MacGregor.


SLED FDBK through SCP slow feedback

     Joe says he doesn’t know what to do with the signals.  He’s going to figure it out.


SIS waveforms archived every hour (plus on change)

     We do want this and around early April

SISDTZ signal updates without archiving

Janice will double check again again.


List of phase 2a signals

Judy, Joe and Janice will meet to discuss what channel database accoutrement are needed tomorrow

Steve/Joe will have a hardware list ready early next week.

Right now, the only ADC channels being used are 0 & 1 (twt5:inp:fwd and twt6:inp:fwd).  If these need to be lobotomized, please let Janice know and she/Joe can move wires around.


macnair module support of aes

Ron is working on this.  Database coming soonish.

Will need to be able to archive and set the gain.


Summary PVs for plc panels? All done.  Yeah, Judy!!!


PLC checkout




Rumored to be coming in a few weeks… Nice email from Alan Hill.  Janice has instructions for what to try when installed and ready to go.



     Looks great!


Realm split

     This is ongoing.  Ops should expect just a few small interruptions in the future.


TR06 is coming…

     Up there on the roof.  Has a processor, ip address and a name.  Not booted with db, etc.



     Still going to be supported.  Spence doesn’t want to support customized C code for routine entries, but if XML-able, then ok.  Next, Bob, Keith, and Spence will discuss wants and work needed.


2-pack PLC coming in April-ish. 

~20 signals as yet undefined.


New Vacuum coming with phase II-a

Judy can get the list from Nancy Spencer and make panels/database/etc.


SIS missing pulses

  Ron please check tr09 acquire button – double check which records are triggered

  If DTZ0 is being triggered, Janice and Joe can plug signals into and see what happens.


Processing order when ACQ is pushed:

process:   TR09:SISDTZ:DISARM

process:   TR09:SISDTZ:FANO0

process:   TR09:SISDTZ:KLY5:CURR:WF

process:   TR09:SISDTZ:KLY6:CURR:WF

process:   TR09:SISDTZ:KLY7:CURR:WF

process:   TR09:SISDTZ:KLY8:CURR:WF

process:   TR09:SISDTZ:MOD:CURR:WF

process:   TR09:SISDTZ:MOD:VOLT:WF

process:   TR09:SISDTZ:FANOSUB0

process:   TR09:SISDTZ:MOD:SPARE01:WF

process:   TR09:SISDTZ:MOD:SPARE02:WF

process:   TR09:SISDTZ:FANO1

process:   TR09:SISDTZ:C1:ARY0:WF

process:   TR09:SISDTZ:C1:BIG0

process:   TR09:SISDTZ:C1:SUB0

process:   TR09:SISDTZ:C1:RMS0

process:   TR09:SISDTZ:C1:ARY1:WF

process:   TR09:SISDTZ:C1:BIG1

process:   TR09:SISDTZ:C1:SUB1

process:   TR09:SISDTZ:C1:RMS1

process:   TR09:SISDTZ:C1:ARY2:WF

process:   TR09:SISDTZ:C1:BIG2

process:   TR09:SISDTZ:C1:SUB2

process:   TR09:SISDTZ:C1:RMS2

process:   TR09:SISDTZ:C1:ARY3:WF

process:   TR09:SISDTZ:C1:BIG3

process:   TR09:SISDTZ:C1:SUB3

process:   TR09:SISDTZ:C1:RMS3

process:   TR09:SISDTZ:C1:ARY4:WF

process:   TR09:SISDTZ:C1:BIG4

process:   TR09:SISDTZ:C1:SUB4

process:   TR09:SISDTZ:C1:RMS4

process:   TR09:SISDTZ:C1:ARY5:WF

process:   TR09:SISDTZ:C1:BIG5

process:   TR09:SISDTZ:C1:SUB5

process:   TR09:SISDTZ:C1:RMS5

process:   TR09:SISDTZ:FANOSUB1

process:   TR09:SISDTZ:C1:ARY6:WF

process:   TR09:SISDTZ:C1:BIG6

process:   TR09:SISDTZ:C1:SUB6

process:   TR09:SISDTZ:C1:RMS6

process:   TR09:SISDTZ:C1:ARY7:WF

process:   TR09:SISDTZ:C1:BIG7

process:   TR09:SISDTZ:C1:SUB7

process:   TR09:SISDTZ:C1:RMS7

process:   TR09:SISDTZ:FANO2

process:   TR09:SISDTZ:C2:ARY0:WF

process:   TR09:SISDTZ:C2:BIG0

process:   TR09:SISDTZ:C2:SUB0

process:   TR09:SISDTZ:C2:RMS0

process:   TR09:SISDTZ:C2:ARY1:WF

process:   TR09:SISDTZ:C2:BIG1

process:   TR09:SISDTZ:C2:SUB1

process:   TR09:SISDTZ:C2:RMS1

process:   TR09:SISDTZ:C2:ARY2:WF

process:   TR09:SISDTZ:C2:BIG2

process:   TR09:SISDTZ:C2:SUB2

process:   TR09:SISDTZ:C2:RMS2

process:   TR09:SISDTZ:C2:ARY3:WF

process:   TR09:SISDTZ:C2:BIG3

process:   TR09:SISDTZ:C2:SUB3

process:   TR09:SISDTZ:C2:RMS3

process:   TR09:SISDTZ:C2:ARY4:WF

process:   TR09:SISDTZ:C2:BIG4

process:   TR09:SISDTZ:C2:SUB4

process:   TR09:SISDTZ:C2:RMS4

process:   TR09:SISDTZ:C2:ARY5:WF

process:   TR09:SISDTZ:C2:BIG5

process:   TR09:SISDTZ:C2:SUB5

process:   TR09:SISDTZ:C2:RMS5

process:   TR09:SISDTZ:FANOSUB2

process:   TR09:SISDTZ:C2:ARY6:WF

process:   TR09:SISDTZ:C2:BIG6

process:   TR09:SISDTZ:C2:SUB6

process:   TR09:SISDTZ:C2:RMS6

process:   TR09:SISDTZ:C2:ARY7:WF

process:   TR09:SISDTZ:C2:BIG7

process:   TR09:SISDTZ:C2:SUB7

process:   TR09:SISDTZ:C2:RMS7

process:   TR09:SISDTZ:REARM


Long term – EPICS control of motors

  Seems to run ok.  How hard to implement for 8pack? (low priority for now)  Module name: OMS… (oregon microsystems page and EPICS supported devices list)  Ron will satiate his curiosity about the module.