8-pack control system working group meeting

10 December 2002

In attendence: Chestnut, Hill, Luchini, Nelson, Rock, S Smith, Young

Notes by: J Nelson

Generic agenda was status of the following:

PLC Checkout

LLRF SW module support

LLRF databases

Testing Plans

Janice and Judy are working on the PLC checkout list. Alan offered to come tomorrow to program the dcm. We decided to hold off until next week when we can talk to Cassel about getting from him the max amount of tables he’ll ever want, so Alan can do his thing for the last time.

Janice will check the allan-bradley website for documentation when she gets a chance for learning how to program the DCM.

ADC SW and databases will be ready by tomorrow afternoon to start some checkout

Kristi will check on the >db buttons on the ADC readbacks.

Janice will make sure all instances of ADC readbacks on epics panels have >db buttons.

Janice and Kristi will make diag displays for the ADC readbacks (PMIN, PMAX, PAVE, etc)

Steve presented a test plan

Step 0: pipe rf generator through IQAs and check out ADCs, DACs, etc. This step includes the ADC/DAC test tomorrow afternoon.

Step 1: Set up 16 200 ns steps

2: Set up calibration

3: Set up A&P calcs

Steve tested many aspects of what already in place. The TRBRs seem to work and changing an I&Q setting changes A&P and vice versa. The plots of something versus timestep all work fine.

What’s missing:

We need 6 variable for each of the 48 IQA channels (6 modules x 8 channels) for calibration. These may be inputs to subroutine variables?

(It’s not clear to me how these values will be used -Janice)

Janice needs to double check the crate layouts in the database and make sure they match with Andy’s plans.

The values on the SLED Control panel need to change the values on the A&P and I&Q control panels. (And vice versa eventually.)

To start, the ampl DAC is the overall amplitude (in volts, not %) times the individual klystron amplitude (in %) times the time step amplitude. Then the ampl DAC in used to calc the I&Q DAC values

The Phase DAC is the timestep phase plus the channel phase for the individual klystron (on the I&Q calibrate panel). Then this DAC is also used in the I&Q DAC calculation.

The plan is to try to do some initial software and hardware checkout tomorrow (Wed) afternoon.

Kukhee/Ron will make sure the SIS real database exists with the right PV names (on the LLRF PV name requirement web page).

It’s not clear to me (Janice) that the DIO database exists at all. Even though we have little buttons on the IQA module panels. When it’s ready, Andy says we can check the hardware with a board that’s already been built. See Dave Anderson if we get to it before the first week of January.

Many DIO buttons are still white – LLRF enable, waveform acquisition (this might be all software, don’t know), etc.

Janice will have the SCP configs ready by next Tuesday.

We still need an engineering decision on what the LLRF Enable button does. Probably from Joe Frisch.