From: Marino Jelavic <mjelavic@silicon-software.com>
To: "Chaiken, Alison" <alison@slac.stanford.edu>
Date: Tue, 31 Aug 2010 05:18:48 -0700
Subject: RE: FPGA Image processing Algorithms
Thread-Topic: FPGA Image processing Algorithms
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 <4C7C3A01.5010402@slac.stanford.edu>
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Hi Dr. Chaiken,

You are correct about pco.edge cameras. We have you on our mailing list and
that is why you received our email. See my answers to your questions
below...

Let me know if you need a quotation.

Best regards,=A0
Marino Jelavic=20
Silicon Software=A0
tel:  514-684-8315=20
fax: 514-822-1033
email:=A0=A0mjelavic@silicon-software.com
web:    http://www.silicon-software.com/


-----Original Message-----
From: Alison Chaiken [mailto:alison@slac.stanford.edu]=20
Sent: Monday, August 30, 2010 7:09 PM
To: Marino Jelavic
Subject: Re: FPGA Image processing Algorithms

Marino Jelavic wrote:
>
> Dear Mrs. Chaiken,
>
As it happens, I am Dr. Chaiken, but you can call me Alison.

> Recently,  we introduced a *PCIe x 4* Camera Link Frame Grabber
>
> that can interface to the fastest Camera Link Camera.
>
Hmm, isn't that the product we are receiving with our pco.edge cameras?
[Marino] Yes it is

> For *real time processing of Image Processing Algorithms*
>
> (IPAs) multiple FPGA boards can be linked to our frame grabber.
>
Is it true that

-- Smart Applets run on the FPGA of the Menable-IV itself, while the=20
Visual Applets can run on a second FPGA?  Therefore the Smart Applets=20
can be interposed in the DMA pipeline before saving the raw data.

-- the Visual Applets could be used for post-processing independently of=20
the framegrabber on an FPGA board in a second, separate host? =20
[Marino] Not correct. Visual Applet can only be used with Silicon Software
products
   The=20
Visual Applets operate on data that has been saved to disk.
[Marino] You can use it in a sort of emulation mode but this is only for
demoing.

If not, I don't understand the difference.     I'd be interested to find=20
out what price ballpark we're talking about for the secondary FPGA boards.
[Marino] Visual Applets give you the general functionality and operators
while Smart Applets give you application related functions ( like blob
analysis ).
The price for secondary FPGA board:
PixelPlant PX100 - 600 $US
[PX 100] Programmable extension board for microEnable=AE IV frame grabber
V-series, FPGA coprocessor
(Xilinx XC3S1600E), 256MB DDRRAM acquisition and image processing buffer,
digital I/O interface.
Compatible with mE4 VD1-CL and mE4 VD4-CL

PixelPlant PX200 - 1200 $US
[PX 200] Programmable extension board for microEnable=AE IV frame grabber
V-series, FPGA coprocessor
(Xilinx XC3S4000), 512MB DDRRAM acquisition and image processing buffer,
digital I/O interface. Compatible
with mE4 VD1-CL and mE4 VD4-CL

[Marino] PixelPlant PX200e -1200 $US
[PX 200e] Programmable extension board for microEnable=AE IV frame grabber
V-series, FPGA coprocessor
(Xilinx XC3S4000), 512MB DDRRAM acquisition and image processing buffer,
digital I/O interface.
Long distance connector. Requires adjacent unoccupied slot. Compatible to
microEnable IV V-series
boards.

--=20
Alison Chaiken				alison@slac.stanford.edu
(650) 926-2755 [checked nearly never]	http://exerciseforthereader.org/
I've got stacks in my structs, I've got arrays in my queues,
I've got the segmentation-violation, core-dumped blues.
-- Rick Moen