This appendix relies heavily on the LAT VME Front-End Communication (Com) Board and the LAT Communications documents mentioned in the References ( References ). Please read these documents before reading this section.
The LAT VME Front-End Communication (Com) Board document describes the VME LAT COMM I/O Board, including its operation and VME registers. The important details for this appendix are:
The VME register for the response FIFO is 32-bits wide.
The physical FIFO is only 18 bits wide, thus only the 18 LSB of the VME register are relevant.
The VME LAT COMM I/O Board can raise a software configurable interrupt when data is ready in the response FIFO.
The LAT Communications document describes a bit serial wire communications protocol (here after LATp) that provides a uniform mechanism for the exchange of any and all information within the LAT.
This appendix specifies a data format for the response FIFO of the VME LAT COMM I/O Board. The format of the data in the response FIFO will follow LATp. The specification is central to the VHDL coding of the COMM Board's FPGA and facilitates read out by flight software.