Log entry time 08:58:44 on August25,2004

Entry number 16

1. I have built a new Digital IO panel.  It has 16 in and 16 out bits.

    Out bit 0  is used to clear the trigger veto latch,

    out bits 1..5 are used for trigger selection.

    in bit 15  is used for triggering the Labview program.

    Out bits 1..10 are T'ed with the correcponding in bits.  The in register is read in

    with each event trigger and written to the event data file (if writing to a file is on),

    so that the state of the out bits 1..5 (the trigger control bits) can be recorded in the

    data file.  When fully implemented the out bits 1..5 will be written to the DIO

    register as the last step in the event handling, as needed for the next event trigger.



2. Presently, there are 3 LRS 2249W, 2 LRS 2259B, and 3 V265 ADC modules

    installed, The LRS modules are in a CAMAC crate and the V265's are in a VME

    crate.  I have setup ADC gate circuits such that each of the CAMAC ADC's has

    a gate controlled independently and all three VME ADC modules are supplied

    the same gate which is controlled independently from the CAMAC ADC gates.

      N     type        gate(ns)

       8     2341A    10000         CAMAC 

       9     2249W   10000         CAMAC

     10     2249W     2000         CAMAC

     11     2249W       200         CAMAC

     12     2259B      1200         CAMAC

     13     2259B      1200         CAMAC

    The gate width for the VME ADC modules is presently set to 5 us.



3. Changes to the event data format in the data file:

3.1 The DIO register integer word is added between the relative time word and the

      integer word from the CAMAC register latch (LRS 2341A module).

3.2 The format of the ADC data from the V265 modules now contains the following:

          bit 0..15 is the ADC data,

          bit 16 when set means that the ADC data is from the 12 bit ADC,

          bit 17 when set means that the ADC data is from the 15 bit ADC,

          bit 18 when set means that the ADC data is from the 12 bit ADC and was

                    scaled by the factor of (30/4),

          when neither bit 16, 17, nor 18 is set the ADC data is from the 15 bit ADC.

      The state of these bits reflects the mode in which the data were handled at the

      read time.  This mode is controlled in the VI which reads the data and can have

      one of these three values:

        Auto   - this is the default. In this mode, if the 15 bit ADC data is less then

                 0xfff, it is used.  Otherwise, the 12 bit ADC data scaled and used.

        12 bit - forces using the 12 bit ADC data (not scaled).

        15 bit - forces using the 15 bit ADC data, regardless of its value.



4. E166net program now gets the MCC and HV data from the E166DAQ Labview program.

   Presently, these data can only be displayed.