In the current plans for the pixel upgrade the data from the chips of one stave will
be sent out through the End of Stave Controller to multiplex into high speed
data transmission with reduced cabling. This location is exposed to extremely
high doses of radiation and the requirement inner most pixel layers extractable
also forces the transmission cable to stay at lower radius for several meters
before exiting PP1. This makes the use of optical fibers for data transfer
problematic. Further more, with the preferred CO2 cooling taking the
system down to lower temperatures, the difficulties with low temperature for
current optical components are also suggesting alternative solutions. Therefore we want to investigate the transfer of data at high rates through coax cable. Things to be checked
include
|
SLAC
| ATLAS@SLAC |
Teststand
To conduct the tests we use a Virtex 4 chip (FX20). This chip has 8 MGT transceivers that are capable of GBit rates.
FPGA logic implements an error bit rate tester running on the MGTs. Initially we use the ML405 Xilinx evaluation boards
for our testing. These boards will be replaced with custom made boards that allow for the use of different types of connectors
by plugging PC boards that carry the connector into the main test board.
Presentations
Documentations and Links
Virtex-4 RocketIO MGT User Guide
ML405 Evaluation Platform, User Guide
Virtex-4 RocketIO Bit-Error Rate Tester
Virtex-4 RocketIO Bit-Error Rate Tester User Guide
ChipScope Pro Serial I/O Toolkit User Guide
ChipScope Pro Software and Cores User Guide
HP54120B Oscilloscope Programmer's Guide for QuickC and QuickBASIC
54120 Series Digitizing Oscilloscope Getting Started Guide