THAP049 (Poster)

Presenter: Roger Flood (Jefferson Lab)
email: hdong@jlab.org
Review Status: Proceedings Ready - 02/01/02
FullText: pdf
Eprint: cs.ar/0111030

A Dual Digital Signal Processor VME Board For Instrumentation And Control Applications*

H. Dong, R. Flood, C. Hovater, J. Musson (JLAB)

A Dual Digital Signal Processing VME Board is being developed for the Continuous Electron Beam Accelerator Facility (CEBAF) Beam Current Monitor (BCM) system at Jefferson Lab. It is a versatile general-purpose digital signal processing board using an open architecture, which allows for adaptation to various applications. The base design uses two independent Texas Instrument (TI) TMS320C6711, which are 900 MFLOPS floating-point digital signal processors (DSP). Applications that require a fixed point DSP can be implemented by replacing the baseline DSP with the pin-for-pin compatible TMS320C6211. Both parallel and serial protocols have been implemented for communicating with off board devices. The initial implementation makes use of TI Multi-channel Serial protocol and VME bus protocol. Other communication protocols can be implemented by re-programming the FPGA. Each DSP is equipped with FLASH PROM and SDRAM for program and data storage. Additionally, each DSP has 16 bits of digital I/O, two digital to analogs converters (DAC), and two analogs to digital converters (ADC). Dual 160 pins mezzanine connectors provide expansion capability without design modifications. The mezzanine interface conforms to the TI Expansion Daughter Card Interface standard. The design can be manufactured with a reduced chip set without redesigning the printed circuit board. For example it can be implemented as a single-channel DSP with no analog I/O. The board supports JTAG 1149 boundary scan to facilitate testing, debugging and programming. It is fully programmable using software development tools such as TI Code Composer Studio and a JTAG emulator such as Spectrum Digital DS510PP_PLUS. Using these tools allows one to program the flash memory and FPGA through the JTAG ports, thus eliminating the need for a separate ROM/FPGA programmer.
{*} This work was supported by the U.S. DOE Contact No DE-AC05-84-ER40150
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Last updated: September 13, 2002

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