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Zilog Z8000

When configured for debugging Zilog Z8000 targets, GDB includes a Z8000
   For the Z8000 family, `target sim' simulates either the Z8002 (the
unsegmented variant of the Z8000 architecture) or the Z8001 (the
segmented variant).  The simulator recognizes which architecture is
appropriate by inspecting the object code.
`target sim ARGS'
     Debug programs on a simulated CPU.  If the simulator supports setup
     options, specify them via ARGS.
After specifying this target, you can debug programs for the simulated
CPU in the same style as programs for your host computer; use the
`file' command to load a new program image, the `run' command to run
your program, and so on.
   As well as making available all the usual machine registers (*note
Registers: Registers.), the Z8000 simulator provides three additional
items of information as specially named registers:
     Counts clock-ticks in the simulator.
     Counts instructions run in the simulator.
     Execution time in 60ths of a second.
   You can refer to these values in GDB expressions with the usual
conventions; for example, `b fputc if $cycles>5000' sets a conditional
breakpoint that suspends only after at least 5000 simulated clock ticks.