ZPD Firmware Synthesis Recipe

If you are returning to this after 2 years away or have never done this before, there are surely details which are not included in these instructions, e.g.software setup issues (licensing, options, libraries, etc...). Hopefully these instructions will provide enough hints about implementing the ZPD firmware that they will jog your memory and you can figure out how to get it working...

Overview

1. Generate the VHDL source files (*.vhd, *.sm, and *.bd → *.vhd)
   Mentor Graphics HDL Design Browser
   Converts source diagrams and VHDL files into pure VHDL for synthesis
2. Compile the generated VHDL
   Mentor Graphics HDL Design Browser
   Compiles the generated VHDL looking for syntax errors or other problems. This step is not stricly necessary, but it is a fast way to check for problems before continuing with synthesis.
3. Synthesize (Generated *.vhd → *.edf)
   Mentor Graphics Leonardo Spectrum
   Convert the VHDL files into specific Virtex-II FPGA components.
4. Implement (*.edf → *.bit)
   Xilinx ISE tools
   Place and route the FPGA components into specific locations and connections in a Virtex-II FPGA. Generate a *.bit file for each design to be combined with others.
5. Create the ACE for for download via a Compact Flash card (*.bit → *.ace)
   Xilinx Impact
   Combine bit files from the Decoder/Driver, Finder/Fitters (A7 and A10 versions), and the Decision Module into a single ACE file for download to the ZPD.

Setup

• FPGA Advantage Setup
• Xilinx Setup

Generation and Compilation

To generate and compile everything, do this for each library (zpd, sergio, fastcontrol, decoderdriver, finder, fitter, decisionmodule, harvard_std):

• Highlight all the design components
  Click on the top component, then hold down the shift key and click on the bottom one.
• Click the Generate button
• Click the Compile button
• Fix any errors
  Errors might just be due to overzealous and buggy type checking in HDL Designer Series -- check the setup hints first if you get errors.
• When generating and compiling, ignore warnings about:
  • variable 'x' is never used
  • after clause will be ignored for synthesis
  • inout 'x' is used for output (input) only
  • interface x has package differences compared to its text view

• In HDL Design Browser, select a top level design in the zpd library.
  E.g. zpd.decoderdriver, zpd.finderfitter, or zpd.decisionmodule
• Generate through components
• Compile through components
• I (Stephen) don't trust HDS's ability to track incremental compiles, so I always make sure that menu items
  • HDL → Set Generate Always
  • HDL → Set Compile Always
  are selected before doing the above steps. But that might just be unnecessary superstition.
• Note that this compile/generate through components won't work for VHDL text components which are included in other VHDL text files instead of being included in a block diagram.

Synthesis

Decoder/Driver

• In HDL Design Browser, select zpd.decoderdriver, then
  • Generate through components
  • Compile through components
  • Click "Synthesis Flow" button
• Confirm the Leonardo settings:
  
  Then click OK. This will run the synthesis.

Finder/Fitter

  HDL files:
    hdl/finder/
    hdl/fitter/
    etc.
  Leo files:
    leo/ff/
    leo/ff/netlists/
    leo/ff/reports/

• Get these TCL files and put them in your leo/ff directory.
• In HDL Design Browser, generate and compile source files
• Start Leonardo Spectrum version 2003a.33 or later
  
  • Leo 2003a comes with FPGAdv 6.1; earlier versions will not work
    (e.g. the version with FPGAdv 5.4 doesn't implement multiplication correctly)
  • Start Leo using the Windows start menu, not from HDL Designer Series
• At the Leo prompt, cd to the leo/ff directory which has the scripts. e.g., cd z:\zpd\leo\ff
• Run the following scripts as needed:
  • source make_megabus_dmem.tcl
  • source make_finder_dmem.tcl
  • source make_fitter_dmem.tcl
  • source make_finder_a10.tcl
  • source make_fitter_a10.tcl
  • source make_ff_a10.tcl
  • source make_finder_a7.tcl
  • source make_fitter_a7.tcl
  • source make_ff_a7.tcl
  You only need to run scripts corresponding to parts of the source VHDL which have changed. E.g., if you make a change to the Finder, you only need to run make_finder_a10.tcl and make_finder_a7.tcl; you do not have to re-synthesize the diagnostic memories, Fitter, etc.
• Time to run: The Finder synthesis will take ~1/2 hour per seedtype; the others run in several minutes or less.

Decision Module

• In HDL Design Browser, select zpd.decisionmodule, then
  • Generate through components
  • Compile through components
  • Click "Synthesis Flow" button
• Confirm the Leonardo settings:
  
  Then click OK. This will run the synthesis.

Implementation

• Create the project if you don't have it setup already
• Highlight the edf source file
• Implement Design
• Generate Programming File

Create the ACE file

• Edit a CDF file to point to the .bit files which you created in previous steps.
• Start Xilinx iMPACT
• Choose the "Load Configuration File" option and load your cdf file.
  
  
  
• This will create a configuration chain like:
  
  
  
• Operations → Generate File

Alternately, you could create the iMPACT project by hand with those bit files in that order and then generate the ace file.