ZPD Fimware Log

---------------------------------------------------------------- 
-- DM 0xe -- 
Aug-20-2004 ew 

Add nhits in the decisionmodule daq data

---------------------------------------------------------------- 
Jul-15-2004 ew 
 
-- DM 0xd , DD 0x16-- 
 
Now "daq_mem" in DM and DD has two views. One for single, the other
for double buffering, and is aiming for an easy switch from single
to double buffering, if needed.

---------------------------------------------------------------- 
Jun-03-2004 ew

-- DM 0xc , DD 0x15--

Placing all machinery for the double buffering in the daq mem,
but still using single buffers 

----------------------------------------------------------------
May-12-2004 sjb

-- DM 0xb --

Fix output diagnostic mem recording.
Implement nMissSeg LUT and cut.


----------------------------------------------------------------
Apr-7-2004 sjb

-- Fitter 7 --
Removed use of buft_vec.
Don't output hitmap for tracks which failed fit.

----------------------------------------------------------------
Apr-5-2004 sjb

-- Fitter 6 --
Uses UserReset again to synchronize steps; stereo_segphi_ram
updated to correctly synchronize upon UserReset.

----------------------------------------------------------------
Mar-31-2004 sjb

-- DD 0x14 --
UserReset is now just a statemachine reset; reframe (cmd 0x14)
resets the DCMs.

----------------------------------------------------------------
Mar-29ish-2004 sjb

-- Finder 5 --
Updated Finder DMem to fix phase jitter bug.

-- DD 0x13 --
UserReset resets FF & DM DCMs via xbus(0)

----------------------------------------------------------------
Mar-18-2004 sjb

-- Finder 4 (still - I should have updated it) --
-- Fitter 5 --
Reorganized memory bus structure to improve Xilinx place & route times

-- DM 0xa --
Updated Fit results memory access due to match changes in the Fitter.

----------------------------------------------------------------
Mar-17-2004 ew

-- DD 0x12 --

Fixing the daq tick trouble (Jan-28-2004) introduced a bug for 
daqformat=2. Now fixed.

----------------------------------------------------------------
Mar-3-2004 sjb

-- Finder 4 --

Added memory addresses with basic params:
  0x110 nRho
  0x111 minPt
  0x112 nDip
  0x113 minDip
  0x114 maxDip
  0x115 phiMerge
  0x116 bField

----------------------------------------------------------------
Feb-24-2004 sjb

-- DD still 0x11 --

DCM phase changed from -72 to -30.  This appears to be the new
magic phase.

----------------------------------------------------------------
Feb-04-2004 sjb

-- DD 0x11 --

Removed secret ability to adjust dlink clock phase with software.
User reset now sends a DCM reset as well.
ZPDi input mask is now 0x1ff (all ZPDi's) instead of just Y1 X2 X3.
Some top level diagram cleanup.

----------------------------------------------------------------
Jan-28-2004 ew

-- DD 0x10 --
-- DM 0x09 --

An attempt to fix the daq tick trouble.

 run start now is latched with a phase against en4 and sent to
the daq block. 

----------------------------------------------------------------
Nov-05-2003 sjb

-- Finder 0x3 --
-- Fitter 0x4 --

Fix IP corr memory addressing.

----------------------------------------------------------------
Nov-05-2003 ew

-- DD     0xf --
-- DM     0x8 --

 Re-define the counter led:

    23:error      22: frame_errr
    21:lock_cclk* 20: lock_dclk*
    19:\          18:\
    17: \         16: \
    15: |         14: |
     .  | A10      .  | A07
     .  | hitmap   .  | hitmap
     .  |          .  |
     3: /          2: /
     1:/           0:/

----------------------------------------------------------------
Oct-28-2003 sjb

-- DD     0xe --
-- Finder 0x2 --
-- Fitter 0x3 --
-- DM     0x7 --

Let's get back into the habit of using this log.
Most recent changes were:
- Disable UserReset to Fitter (Fitter 3)
- Fix DAQ segMask[15:0] phase bug wrt other segMask bits (DD 0xe)
  Also added block 1 memory addresses 0x11 to 0x2f in DD 0xe.

----------------------------------------------------------------
Oct-30-2003 sjb

-- Finder 0x3 --
-- Fitter 0x4 --

finder.finder_top : version 3
finder.close_seg_finder : pipeline seg_num while finding closest segs before
  sending it to the Fitter as the seed_num.  The current implementation
  effectively has this inverted.  This pipeline fix will be more robust against
  pipeline timing changes than a simple inversion would.

fitter.r_phi_fit_calc : change ipcorr_addr to be (seed_num & seg_index)
  instead of (seg_index & seed_num).  This makes a more natural address order
  for the LUT software.

zpd.finderfitter : fitter version 4.



----------------------------------------------------------------
Jul-23-2003

-- DD version 0x9 --

sergio.sergio_top (new version number 9)                                        
sergio.input_sync (new frame bit mask order 8:0 -> y2:0,x5:0)                   
fastcontrol.clk_output (generic constant control of proto_zpdi for TTL          
vs. LVDS clk output)                                                            
zpd.decoderdriver (uses generic const to control proto_zpdi...)          

----------------------------------------------------------------
Jun-20-2003

-- DD version 0x8 --

Components to update:                                                           
                                                                                
zpd.decoderdriver                                                               
fastcontrol.fastcontrol_top                                                     
sergio.input_sync                                                               
sergio.sergio_top                                                               
sergio.latch_err (new component)                                                
                                                                                
Also, add the following lines to your decoderdriver.ucf file:                   
                                                                                
NET "serialbit(0)" LOC = "af2";                                                 
NET "serialbit(1)" LOC = "ae2";                                                 
NET "serialbit(2)" LOC = "ad2";                                                 
NET "serialbit(3)" LOC = "ac2";                                                 
These changes add:                                                              
- Expected TSF mask register at block 1 address 0x10                            
- Frame error sent to glink sync error bit of CSR 1, latched for 64             
events                                                                          
- Other errors sent to glink lock error bit of CSR 1, latched for 64            
events                                                                          
- Sergio version number 8                                                       
- Upper nybble of sergio version number register (block 1 address 0) is         
the board serial number                                                         

clk_input has the default phase value of -72 for dclk
                         
----------------------------------------------------------------
Jun-11-2003

-- DD version 0x7 --

Activate dlink_almost_out

----------------------------------------------------------------
May-28-2003

-- DM version 0x5 --
 DAQ memory address shift found by Gerald fixed.
 This was introduced when a switch from the self pattern generation 
 to the normal operation mode was made. 

-- DD version 0x6 --
 Bug in op_address producing "badd" for DAQ memory reading fixed.
 This was a piece of logic left there from old TSF to count the 
 playback memory location as to replicate the memory_active logic 
 to feed the CSR readback (from Su Dong).

----------------------------------------------------------------
May-19-2003

-- DM version 0x4 --
 Decision bits stretched to three clk8 period.
 Removing self pattern generation function from the daq memory and 
 accepting fit results.

-- DD version 0x5 --
 Removing self pattern generation function from the daq memory and 
 accepting segments from TSF.