SLAC PEP-II
BABAR
SLAC<->RAL
Babar logo
HEPIC E,S & H Databases PDG HEP preprints
Organization Detector Computing Physics Documentation
Personnel Glossary Sitemap Search Hypernews
Unwrap page!
Det. Search
Who's who?
Meetings
FAQ
Images
Archive
Systems
Performance
Intern. region
Vertex Tracker
Drift chamber
DIRC
Calorimeter
IFR
LST
Magnet
Electronics
Trigger
Operations
Run Coordination
Contact Experts
Shift Takers Info
Operations Manual
Electronic Logbook
Ops Hypernews
Shift Signup
Check this page for HTML 4.01 Transitional compliance with the
W3C Validator
(More checks...)

How to Adjust the ZPD DLink Phase

The BaBar DAQ system is a bit picky about the phase of the dlink data. Simply clocking with the dclk isn't enough, since the ZPD does this internal to the Decoder/Driver FPGA which produces different delays than the BLT which uses an external chip. The ZPD firmware must adjust the dclk phase to hit the magic sweet spot that matches the BLT. Here's how to do that:

The dclk phase is adjusted in fastcontrol/clk_input which is included on the top level diagram of zpd/decoderdriver. The relevant part is:

  attribute phase_shift of dclk_dcm : label is -30;
That phase runs -128 to 127. When the sweet spot is found, it should be entered here.

When searching for the sweet spot, it is a hassle to have to go through the entire generation/synthesis/implementation cycle to test a new value. Here's how you can try a new value by editing the post-implementation Xilinx files:

  • In the Xilinx Project Navigator, open a Decoder/Driver project and implement it if you haven't already done so.
  • Double click on "View/Edit Routed Design (FPGA Editor)"


  • On the right is a button called "editmode". Click this until "Read Write" appears in the status bar in the lower right hand corner of the main window.
  • In the "List1" subwindow, change the Name Filter to *dcm* and click Apply.
  • Highlight the item with a name like "I21_dclk_dcm" and then click on the "Zoom Selection" button on the toolbar.
  • Double click the red highlighted DCM component. This will pop up a component editor window.
  • Click the "begin editing" button on the toolbar.
  • Click the Show/Hide Attributes button on the toolbar
  • Change the PHASE_SHIFT to a new value.
  • Click the Apply toolbar button and close the component editor window.
  • Click the Save toolbar button of the main window.
  • Exit the FPGA Editor.
  • Back in the Xilinx Project Navigator, generate the programming file and then use iMPACT to create the ACE file, etc.

That may seem like a lot of steps, but it is a lot fewer than if you had to start from a change in the VHDL source code.