TSF Memory Map
Memory Map for TSF Memories (Subject to Revision as I sort things out..)
-- This is the version that exists in the test firmware --
InMem : 0x000000-0x03FFFF -- (1 Megabyte)
OutMem : 0x040000-0x07FFFF -- (1 Megabyte)
Mask_Pos : 0x080000-0x080050 -- (8 bit address range,40*16bits) -- These are changing.
Mask_Neg : 0x080080-0x0800D0 -- (8 bit address range,40*16bits) -- These are changing.
Version 1 : 0x0C0000-0xC00000 -- Just 32bit long
Version 2 : 0x0D0000-0xD00000 -- Just 32bit long
Version 3 : 0x0E0000-0xE00000 -- Just 32bit long
Version FOD : 0x100000-0x100000-- Just 32bit long
Version IN : 0x110000-0x110000-- Just 32bit long
Constant 1 : 0x140000-0x140000 -- Just 32bit long
Constant 2 : 0x150000-0x150000 -- Just 32bit long
Constant 3 : 0x160000-0x160000 -- Just 32bit long
Constant FOD : 0x180000-0x180000 -- Just 32bit long
Constant IN : 0x190000-0x190000 -- Just 32bit long
FPGA1 LUT1 : 0x200000-0x23FFFF -- (1 Megabyte)
FPGA1 LUT2 : 0x240000-0x27FFFF -- (1 Megabyte)
FPGA2 LUT1 : 0x280000-0x2BFFFF -- (1 Megabyte)
FPGA2 LUT2 : 0x2C0000-0x2FFFFF -- (1 Megabyte)
FPGA3 LUT1 : 0x300000-0x33FFFF -- (1 Megabyte)
FPGA3 LUT2 : 0x340000-0x37FFFF -- (1 Megabyte)
The large memories are 32bits wide... so remember that
or
interesting things
(TM) will happen..
***FLASH***
The Mask memory is 16 bits wide, but is done as follows..
Address 0 = layer zero
lower 16bits.
Address 1 = layer zero
upper 16bits.
and so on upto layer 40.
The highst bit is the
27th. Others are ignored.
The default is for both Positive and negative masks to be zerro..
So we are not doing any masking
Idea behind Address System.
Basicly the lower 2 bits of BlockAddress and all 16bits of Address are
used to form addresses.
The bits 5 downto 2 of Block Address are used to select which ram to
talk to. It looks like this.
xxxxxxxxxxBBBBAA
AAAAAAAAAAAAAAAA
B = Block Address/
Memory Selection
A = Memory Address
The Version and Constant
memories are in each FPGA, not sure if they are needed everywhere, but
there will be space for them..
For Playback record, mem 1 is input, mem 2 is output (BLT/ZPD combined)
and mem 3 is neighbour. So it will be possible to use live data as
input, with prerecorded neighbour data. It will also be possible to
record neighbour seperate from normal data..BUT YOU CAN'T DO PLAY DATA
AND RECORD NEIGHBOUR.. not in this version at least. The same goes for
output.. Play or Record of ZPD and BLT are linked.. you cannot play
one,
and record another.
- ZPD Data is stored in the lower 21 bits of the Output
Mem
- BLT Data is stored in the bits 28,29,30,31 or the
Output Mem
- The frame pulse is also recorded, but not used when
in playback as we sync to clock4
- BLT Data is recorded every clock60, so you have to
take that into account when you process the BLT data after reading it
out, or when loading it in! Use 2 memory locations per BLT Word of data.
- Input data is stored in the lower 20bits of the Input
- Neighbour data is stored in the bits 21-27 of the
first 4 words of a frame.
Constant Memories.
FOD & Input:
When in playback or record
mode you man not wish to
use the full memory size. So they are resizable on the fly. There are 2
"Constant" memories in these chips,
these hold the memory high address pointer. This pointer is the highest
memory location to play or record. Memory starts at location 0, so to
play N words, write N-1 into the location. Most things work in 16 word
frames. So 0xF, 0x1F etc are correct values. If you write a different
value, you may get strange results. Values of 0x0 are converted into
something sensible by the firmware. DO NOT RELY on any default values,
always set this!!
Engines:
The constant memory here is
the DAQ offset in clk4's from the current position, usually set by the
configure.
Input Memory Frame Data
Layout
| Clock
Tick |
Neighbour
Data (IN)
|
GLink
Data
|
Bit
Positions
|
26
downto 20
|
19
downto 0
|
1
|
7
bits (27 downto 21) |
20bits
|
2
|
7
bits (20 downto 14)
|
20bits |
3
|
7
bits (13 downto 7)
|
20bits |
4
|
7
bits (6 downto 0)
|
20bits |
5
|
--none-- |
20bits |
6
|
--none-- |
20bits |
7
|
--none-- |
20bits |
8
|
--none-- |
20bits |
9
|
--none-- |
20bits |
10
|
--none-- |
20bits |
11
|
--none-- |
20bits |
12
|
--none-- |
20bits |
13
|
--none-- |
20bits |
14
|
--none-- |
20bits |
15
|
--none-- |
20bits |
16
|
--none-- |
20bits |
Output Memory Frame
We Have a slightly
different convention to the ZPD, we start out play/record on a clock 4
edge, with a framebit, its basicly the ZPD data format, but with the 16
word window slid down one word. When in run mode things are a
continious stream, and you are getting frame bits every 16 clock60's.
In order to slip any recoded data into the stream correctly, you need a
frame bit in the first word, also, when you record you will get the
same..
|
Clock
Tick
|
BLT
Data
|
ZPD
Data
|
FrameBit
|
Discription
|
|
Bit
Positions
|
31
downto 28
|
21
downto1
|
0
|
|
Clock4 Edge
|
0
|
4
bits (1st word)
|
21
bits
|
1
bit
|
Frame
Bit
|
|
1
|
4
bits (1st word) |
21
bits |
1
bit |
Seg
Mask
|
|
2
|
4
bits (2nd word) |
21
bits |
1
bit |
Loc[3]
|
|
3
|
4
bits (2nd word) |
21
bits |
1
bit |
Loc[2]
|
|
4
|
4
bits (3rd word) |
21
bits |
1
bit |
Loc[1]
|
|
5
|
4
bits (3rd word) |
21
bits |
1
bit |
Loc[0]
|
|
6
|
4
bits (4th word) |
21
bits |
1
bit |
Phi[5]
|
|
7
|
4
bits (4th word) |
21
bits |
1
bit |
Phi[4]
|
|
8
|
4
bits (1st word) |
21
bits |
1
bit |
Phi[3]
|
|
9
|
4
bits (1st word) |
21
bits |
1
bit |
Phi[2] |
|
10
|
4
bits (2nd word) |
21
bits |
1
bit |
Phi[1] |
|
11
|
4
bits (2nd word) |
21
bits |
1
bit |
Phi[0] |
|
12
|
4
bits (3rd word) |
21
bits |
1
bit |
dPhi[2]
|
|
13
|
4
bits (3rd word) |
21
bits |
1
bit |
dPhi[1]
|
|
14
|
4
bits (4th word) |
21
bits |
1
bit |
dPhi[0]
|
|
15
|
4
bits (4th word) |
21
bits |
1
bit |
--
NULL--
|
Page author: Marc Kelly
| Last significant update:
March-10-2004 |
|
