The ZPD -> GLT interface map Su Dong Mar/18/04 ============================ ZPD output: D[0:5] -> ZPDi GLTD[0:5] D[6:7] terminated at ZPDi GLT transmitter Interface: ZPDi GLTi in GLTi mux_out Backplane GLT logic ---- ------- ------------ --------- --------- ZPD0 GLTD0 ZPDA0 MUX_AP1 AP1 AP0 GLTD1 ZPDA1 MUX_AP2 AP2 AP1 GLTD2 ZPDA2 MUX_X0 X0 X0 GLTD3 ZPDA3 MUX_X8 X8 X8 GLTD4 ZPDA4--OR--MUX_X16 X16 X16 GLTD5 ZPDA5 | ZPD1 GLTD0 ZPDB0 | MUX_AP3 AP3 AP2 GLTD1 ZPDB1 | MUX_AP4 AP4 AP3 GLTD2 ZPDB2 | MUX_X1 X1 X1 GLTD3 ZPDB3 | MUX_X9 X9 X9 GLTD4 ZPDB4--- GLTD5 ZPDB5 ZPD2 GLTD0 ZPDC0 MUX_AP5 AP5 AP4 GLTD1 ZPDC1 MUX_AP6 AP6 AP5 GLTD2 ZPDC2 MUX_X2 X2 X2 GLTD3 ZPDC3 MUX_X10 X10 X10 GLTD4 ZPDC4--OR--MUX_X17 X17 X17 GLTD5 ZPDC5 | ZPD3 GLTD0 ZPDD0 | MUX_AP7 AP7 AP6 GLTD1 ZPDD1 | MUX_AP8 AP8 AP7 GLTD2 ZPDD2 | MUX_X3 X3 X3 GLTD3 ZPDD3 | MUX_X11 X11 X11 GLTD4 ZPDD4--- GLTD5 ZPDD5 ZPD4 GLTD0 ZPDE0 MUX_AP9 AP9 AP8 GLTD1 ZPDE1 MUX_AP10 AP10 AP9 GLTD2 ZPDE2 MUX_X4 X4 X4 GLTD3 ZPDE3 MUX_X12 X12 X12 GLTD4 ZPDE4--OR--MUX_X18 X18 GLTD5 ZPDE5 | ZPD5 GLTD0 ZPDF0 | MUX_AP11 AP11 AP10 GLTD1 ZPDF1 | MUX_AP12 AP12 AP11 GLTD2 ZPDF2 | MUX_X5 X5 X5 GLTD3 ZPDF3 | MUX_X13 X13 X13 GLTD4 ZPDF4--- GLTD5 ZPDF5 ZPD6 GLTD0 ZPDG0 MUX_AP13 AP13 AP12 GLTD1 ZPDG1 MUX_AP14 AP14 AP13 GLTD2 ZPDG2 MUX_X6 X6 X6 GLTD3 ZPDG3 MUX_X14 X14 X14 GLTD4 ZPDG4--OR--MUX_X19 X19 X19 GLTD5 ZPDG5 | ZPD7 GLTD0 ZPDH0 | MUX_AP15 AP15 AP14 GLTD1 ZPDH1 | MUX_AP0 AP0 AP15 GLTD2 ZPDH2 | MUX_X7 X7 X7 GLTD3 ZPDH3 | MUX_X15 X15 X15 GLTD4 ZPDH4--- GLTD5 ZPDH5 Note: For AP input from PTD, because PTD0 is covering sectors 15/16,0/16 in phi instead of the naive 0/16,1/16, GLT input FPGA internally is making the phi rotation shift: backplane pin GLT logic AP0 -> AP15 AP1 -> AP0 ... ... AP15 -> AP14 Due to this hardwired corection in the GLT, the new input from ZPD (which is formatted as 0/1,2/3 etc pairs) for replacing the old PTD A' needs to be counter-rotated to mimic PTD phi map so that the GLT rotation correction will restore them to the right origial form.