ZPDi TSF segment->ZPD backplane switch map ========================================== Signal geometrical naming convention: Xsector-Layer-Segment e.g. X3-V3-2 mean sector X0 Superlayer V3 segment 2 (0-2). For convenience, we actually split up the TSFY sectors in a similar way to follow the TSFX sector naming. So that e.g. X1-U5-0/2 corresponds to Y1-U5-3/5. Swicth TSF LVDS ZPDi ZPD FPGA Sector S-cell channel Switch Signal ------ ------- ------- ------- ------ ------ 1 X0-A1-0 X0-A1-0 X0-01 1-S00 S000 X0-A1-1 X0-A1-1 X0-02 1-S01 S001 X0-A1-2 X0-A1-2 X0-03 1-S02 S002 X0-U2-0 X0-U2-0 X0-04 1-S03 S003 X0-U2-1 X0-U2-1 X0-05 1-S04 S004 X0-U2-2 X0-U2-2 X0-06 1-S05 S005 X0-V3-0 X0-V3-0 X0-07 1-S06 S006 X0-V3-1 X0-V3-1 X0-08 1-S07 S007 X0-V3-2 X0-V3-2 X0-09 1-S08 S008 X0-U5-0 Y0-U5-0 Y0-00 1-S09 S009 X0-U5-1 Y0-U5-1 Y0-01 1-S10 S010 X0-U5-2 Y0-U5-2 Y0-02 1-S11 S011 X0-U8-0 X0-U8-0 X0-13 1-S12 S012 X0-U8-1 X0-U8-1 X0-14 1-S13 S013 X0-U8-2 X0-U8-2 X0-15 1-S14 S014 1 X1-A1-0 X1-A1-0 X1-01 1-S15 S015 X1-A1-1 X1-A1-1 X1-02 1-S16 S016 X1-A1-2 X1-A1-2 X1-03 1-S17 S017 X1-U2-0 X1-U2-0 X1-04 1-S18 S018 X1-U2-1 X1-U2-1 X1-05 1-S19 S019 X1-U2-2 X1-U2-2 X1-06 1-S20 S020 X1-V3-0 X1-V3-0 X1-07 1-S21 S021 X1-V3-1 X1-V3-1 X1-08 1-S22 S022 X1-V3-2 X1-V3-2 X1-09 1-S23 S023 X1-A4-0 X1-A4-0 X1-10 1-S24 S024 X1-A4-1 X1-A4-1 X1-11 1-S25 S025 X1-A4-2 X1-A4-2 X1-12 1-S26 S026 X1-U5-0 Y0-U5-3 Y0-04 1-S27 S027 X1-U5-1 Y0-U5-4 Y0-05 1-S28 S028 X1-U5-2 Y0-U5-5 Y0-06 1-S29 S029 X1-V6-0 Y0-V6-3 Y0-10 1-S30 S030 X1-V6-1 Y0-V6-4 Y0-11 1-S31 S031 X1-V6-2 Y0-V6-5 Y0-12 1-S32 S032 X1-A7-0 Y0-A7-3 Y0-16 1-S33 S033 X1-A7-1 Y0-A7-4 Y0-17 1-S34 S034 X1-A7-2 Y0-A7-5 Y0-18 1-S35 S035 X1-U8-0 X1-U8-0 X1-13 1-S36 S036 X1-U8-1 X1-U8-1 X1-14 1-S37 S037 X1-U8-2 X1-U8-2 X1-15 1-S38 S038 X1-V9-0 X1-V9-0 X1-16 1-S39 S039 X1-V9-1 X1-V9-1 X1-17 1-S40 S040 X1-V9-2 X1-V9-2 X1-18 1-S41 S041 X1-A10-0 X1-A10-0 X1-19 1-S42 S042 X1-A10-1 X1-A10-1 X1-20 1-S43 S043 X1-A10-2 X1-A10-2 X1-21 1-S44 S044 ---------------------------------------------- 2 X2-A1-0 X2-A1-0 X2-01 2-S00 S045 X2-A1-1 X2-A1-1 X2-02 2-S01 S046 X2-A1-2 X2-A1-2 X2-03 2-S02 S047 X2-U2-0 X2-U2-0 X2-04 2-S03 S048 X2-U2-1 X2-U2-1 X2-05 2-S04 S049 X2-U2-2 X2-U2-2 X2-06 2-S05 S050 X2-V3-0 X2-V3-0 X2-07 2-S06 S051 X2-V3-1 X2-V3-1 X2-08 2-S07 S052 X2-V3-2 X2-V3-2 X2-09 2-S08 S053 X2-A4-0 X2-A4-0 X2-10 2-S09 S054 X2-A4-1 X2-A4-1 X2-11 2-S10 S055 X2-A4-2 X2-A4-2 X2-12 2-S11 S056 X2-U5-0 Y1-U5-0 Y1-01 2-S12 S057 X2-U5-1 Y1-U5-1 Y1-02 2-S13 S058 X2-U5-2 Y1-U5-2 Y1-03 2-S14 S059 X2-V6-0 Y1-V6-0 Y1-07 2-S15 S060 X2-V6-1 Y1-V6-1 Y1-08 2-S16 S061 X2-V6-2 Y1-V6-2 Y1-09 2-S17 S062 X2-A7-0 Y1-A7-0 Y1-13 2-S18 S063 X2-A7-1 Y1-A7-1 Y1-14 2-S19 S064 X2-A7-2 Y1-A7-2 Y1-15 2-S20 S065 X2-U8-0 X2-U8-0 X2-13 2-S21 S066 X2-U8-1 X2-U8-1 X2-14 2-S22 S067 X2-U8-2 X2-U8-2 X2-15 2-S23 S068 X2-V9-0 X2-V9-0 X2-16 2-S24 S069 X2-V9-1 X2-V9-1 X2-17 2-S25 S070 X2-V9-2 X2-V9-2 X2-18 2-S26 S071 X2-A10-0 X2-A10-0 X2-19 2-S27 S072 X2-A10-1 X2-A10-1 X2-20 2-S28 S073 X2-A10-2 X2-A10-2 X2-21 2-S29 S074 2 X3-A1-0 X3-A1-0 X3-01 2-S30 S075 X3-A1-1 X3-A1-1 X3-02 2-S31 S076 X3-A1-2 X3-A1-2 X3-03 2-S32 S077 X3-U2-0 X3-U2-0 X3-04 2-S33 S078 X3-U2-1 X3-U2-1 X3-05 2-S34 S079 X3-U2-2 X3-U2-2 X3-06 2-S35 S080 X3-V3-0 X3-V3-0 X3-07 2-S36 S081 X3-V3-1 X3-V3-1 X3-08 2-S37 S082 X3-V3-2 X3-V3-2 X3-09 2-S38 S083 X3-A4-0 X3-A4-0 X3-10 2-S39 S084 X3-A4-1 X3-A4-1 X3-11 2-S40 S085 X3-A4-2 X3-A4-2 X3-12 2-S41 S086 ^ X3-U5-0 Y1-U5-3 Y1-04 2-S42 S087 | X3-U5-1 Y1-U5-4 Y1-05 2-S43 S088 J2 ---------- X3-U5-2 Y1-U5-5 Y1-06 2-S44 S089 J3 X3-V6-0 Y1-V6-3 Y1-10 2-S45 S090 | X3-V6-1 Y1-V6-4 Y1-11 2-S46 S091 V X3-V6-2 Y1-V6-5 Y1-12 2-S47 S092 X3-A7-0 Y1-A7-3 Y1-16 2-S48 S093 X3-A7-1 Y1-A7-4 Y1-17 2-S49 S094 X3-A7-2 Y1-A7-5 Y1-18 2-S50 S095 X3-U8-0 X3-U8-0 X3-13 2-S51 S096 X3-U8-1 X3-U8-1 X3-14 2-S52 S097 X3-U8-2 X3-U8-2 X3-15 2-S53 S098 X3-V9-0 X3-V9-0 X3-16 2-S54 S099 X3-V9-1 X3-V9-1 X3-17 2-S55 S100 X3-V9-2 X3-V9-2 X3-18 2-S56 S101 X3-A10-0 X3-A10-0 X3-19 2-S57 S102 X3-A10-1 X3-A10-1 X3-20 2-S58 S103 X3-A10-2 X3-A10-2 X3-21 2-S59 S104 ----------------------------------------------- 3 X4-A1-0 X4-A1-0 X4-01 3-S00 S105 X4-A1-1 X4-A1-1 X4-02 3-S01 S106 X4-A1-2 X4-A1-2 X4-03 3-S02 S107 X4-U2-0 X4-U2-0 X4-04 3-S03 S108 X4-U2-1 X4-U2-1 X4-05 3-S04 S109 X4-U2-2 X4-U2-2 X4-06 3-S05 S110 X4-V3-0 X4-V3-0 X4-07 3-S06 S111 X4-V3-1 X4-V3-1 X4-08 3-S07 S112 X4-V3-2 X4-V3-2 X4-09 3-S08 S113 X4-A4-0 X4-A4-0 X4-10 3-S09 S114 X4-A4-1 X4-A4-1 X4-11 3-S10 S115 X4-A4-2 X4-A4-2 X4-12 3-S11 S116 X4-U5-0 Y2-U5-0 Y2-01 3-S12 S117 X4-U5-1 Y2-U5-1 Y2-02 3-S13 S118 X4-U5-2 Y2-U5-2 Y2-03 3-S14 S119 X4-V6-0 Y2-V6-0 Y2-07 3-S15 S120 X4-V6-1 Y2-V6-1 Y2-08 3-S16 S121 X4-V6-2 Y2-V6-2 Y2-09 3-S17 S122 X4-A7-0 Y2-A7-0 Y2-13 3-S18 S123 X4-A7-1 Y2-A7-1 Y2-14 3-S19 S124 X4-A7-2 Y2-A7-2 Y2-15 3-S20 S125 X4-U8-0 X4-U8-0 X4-13 3-S21 S126 X4-U8-1 X4-U8-1 X4-14 3-S22 S127 X4-U8-2 X4-U8-2 X4-15 3-S23 S128 X4-V9-0 X4-V9-0 X4-16 3-S24 S129 X4-V9-1 X4-V9-1 X4-17 3-S25 S130 X4-V9-2 X4-V9-2 X4-18 3-S26 S131 X4-A10-0 X4-A10-0 X4-19 3-S27 S132 X4-A10-1 X4-A10-1 X4-20 3-S28 S133 X4-A10-2 X4-A10-2 X4-21 3-S29 S134 3 X5-A1-0 X5-A1-0 X5-01 3-S30 S135 X5-A1-1 X5-A1-1 X5-02 3-S31 S136 X5-A1-2 X5-A1-2 X5-03 3-S32 S137 X5-U2-0 X5-U2-0 X5-04 3-S33 S138 X5-U2-1 X5-U2-1 X5-05 3-S34 S139 X5-U2-2 X5-U2-2 X5-06 3-S35 S140 X5-V3-0 X5-V3-0 X5-07 3-S36 S141 X5-V3-1 X5-V3-1 X5-08 3-S37 S142 X5-V3-2 X5-V3-2 X5-09 3-S38 S143 X5-A4-0 X5-A4-0 X5-10 3-S39 S144 X5-A4-1 X5-A4-1 X5-11 3-S40 S145 X5-A4-2 X5-A4-2 X5-12 3-S41 S146 X5-V6-0 Y2-V6-3 X2-10 3-S42 S147 X5-V6-1 Y2-V6-4 X2-11 3-S43 S148 X5-V6-2 Y2-V6-5 X2-12 3-S44 S149 X5-V9-0 X5-V9-0 X5-16 3-S45 S150 X5-V9-1 X5-V9-1 X5-17 3-S46 S151 X5-V9-2 X5-V9-2 X5-18 3-S47 S152 Frame bit assignement: ---------------------- Currently the pin names are labelled on the J1 as a b c Row 2 spare0 spare1 spare2 (have to check which spare is clock60) Row 3 frame8 frame7 frame6 Row 4 frame5 frame4 frame3 Row 5 frame2 frame1 frame0 Spec: Prototype actual where frame0 = X0 X1 frame1 = Y0 Y0 frame2 = X1 X0 frame3 = X2 X3 frame4 = Y1 Y1 frame5 = X3 X2 frame6 = X4 X5 frame7 = Y2 Y2 frame8 = X5 X4