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DCT Upgrade TSF Slow Monitoring
Last update: May/01/02 Su Dong
The TSF slow monitoring is provided through a MUX on the TSFi which keeps
6-7 lines of status info from which 1 signal can be selected at a time
and readout. The I/O to the external world is via the
P3 (DIRC) backplane.
Some of the relevant signals on P3 for slow monitoring:
| SV | Sensor Voltage. The voltage value represent the status
of various slow monitoring variables. For TSF, this is mainly the GLINK
related quantities. |
| GA(0:3) | Global Address. The DIRC documentation called this
Crate Address. While this is really the FEE slot numbers hardwired uniquely
for each slot. |
| A(0:7) | Address driven by slow monitoring to select the
desired channel in the desired slot (one channel at a time).
A(0:3)=channel number;
A(4:7) slot address (GA). |
Due to time pressure for commissioning the existing system, the slow
monitoring part of the TSF system was somewhat klugy. The following
is the block diagram for the existing TSFi:
Because only one set of 4-bit `Global Address' lines are brought to
the TSFi, it actually had to carry the A(4:7) dynamic slot address
instead, using a jumper on the TSF P3 to take the A(4:7) lines to
the `GA' lines for the TSFi. While the actual hardwired slot address
was duplicated with the board ID rotary switch on the TSFi to compared
with the A(4:7) address carried over via the `GA' lines on P1.
The best way to remove this kluge and without
an board dependent switch on each TSFi and avoiding redirect both
A and GA back out to TSFi through P1, is to include the address
comparion logic in the TSF input FPGA using the readily available
GA from P3 without the need to redirect them back out the P1 backplane
to TSFi. This revised scheme would diagramatically look like the following:
This should neither stretch the pin count nor the FPGA utilization
and with the benefit of only one line of slot select decision back
out to TSFi. The corresponding new TSFi/TSF interface then could
look like:
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