ZPD->GLT Scope test  --- May 19-20,2003

1. playback output memory

   CLINK and D0 signal :channel 1 is GLT TP2, channel 2 is GLT J1 pin12  

CLK 8 and D0 signal : channel 1 is GLT TP8, channel 2 is GLT J1  pin12

2.   time relation between CLINK and CLK8 and D0 for playback fit results.

       test contidition:  At Decision Module (0x8000), set all 0xfffs to 0x4000-0x45ff   , except setting 0x0 to address 0x4000-0x4003,0x4200-0x4203,0x4400-4403

• play continuous

          The time delay before and after interface board: 

          ZPD Decision signal bit 0 -- channel 1  signal is at GLT J1 pin12, channel 2 signal is at  ZPD J2 pin30

            clock 8 and D0 signal: channel 1 is GLT TP8,  channel is at ZPD J2 pin30

• single shot playback

          clock 8 and D0 signal: channel 1 is GLT TP8,  channel 2 is at ZPD J2 pin30

       clock 8 and D0 signal: channel 1 is GLT TP8,  channel 2 is at GLT J1 pin12

    CLINK and D0 signal: channel 1 is GLT TP2 , channel 2 is at ZPD J2 pin30

3.D0 signal on GLTi between receiver and XLINX chip:

• with 220 ohm termination at input of receiver

• without 220 ohm termination at input of receiver