TSF->ZPD Interface scope test Apr/30/03
Scope trace done with TSF 1-chip board and ZPD in same crate.
3 LVDS cables are mostly conneceted to the 3 channels on ZPDi switch-3.
50 Ohm resister damping already in place. TSFi firmware from
Jeff's Par/30 version, but before the frame-bit drive from delayed
_i signal fix. ZPDi firmware just after Xuedong changed to drive
all output to ZPD on falling edge of TSF clocks. Among the 4 scope
probes, channel 1 (yellow) probe appears to have some problem which
sometime affects the amplitude and sometimes introduce an DC offset.
TSFi: TSF input clock and frame bit
- CH1 (yellow) = TSFi TP3 input TSF clock just after LVDS receiver.
- CH2 (green) = TSFi TP1 input TSF frame bit
TSFi: Frame bits at various stages
- CH1 (yellow) = TSFi TP3 input TSF frame bit just after LVDS receiver.
- CH2 (green) = TSFi TP1 input TSF clock
- CH3 (blue) = TSFi TP4 Frame-B after fanout Xilinx
- CH4 (pink) = TSFi TP2 Frame-A after fanout Xilinx
(CH3,CH4 used slower Tek P611B probes just for this picture, before
Xuedong found the other 2 faster probes in the scope bag)
TSFi/ZPDi: Clocks before and after LVDS channel link
- CH1 (yellow) = ZPDi TP9 X4 clock before switch
- CH2 (green) = TSFi TP1 input TSF clock
- CH3 (blue) = ZPDi TP4 Y2 clock before switch
- CH4 (pink) = ZPDi TP14 X5 clock before switch
(There was substantial jitter ~4ns level between fanout clocks after
LVDS channel link receiver on the ZPDi side, and the TSF input clock)
TSFi/ZPDi: Frame bits before and after LVDS channel link
- CH1 (yellow) = ZPDi TP10 X4 Frame bit before switch
- CH2 (green) = TSFi TP4 Frame-B
- CH3 (blue) = ZPDi TP8 Y2 Frame bit before switch
- CH4 (pink) = ZPDi TP18 X5 Frame bit before switch
ZPDi: Clocks before and after Switch XilinX
- CH1 (yellow) = ZPDi TP27 X4 clock after switch
- CH2 (green) = ZPDi TP4 Y2 clock before switch
- CH3 (blue) = ZPDi TP24 Y2 clock after switch
- CH4 (pink) = ZPDi TP21 X5 clock after switch
ZPDi: Frame bits before and after Switch XilinX
- CH1 (yellow) = ZPDi TP27 X4 Frame bits after switch
- CH2 (green) = ZPDi TP8 Y2 Frame bits before switch
- CH3 (blue) = ZPDi TP24 Y2 Frame bits after switch
- CH4 (pink) = ZPDi TP21 X5 Frame bits after switch
ZPDi: Frame bits/clock timing before Switch XilinX
- CH2 (green) = ZPDi TP4 Y2 clock before switch
- CH3 (blue) = ZPDi TP8 Y2 Frame bits before switch
ZPDi: Frame bit/clock timing after Switch XilinX
- CH2 (green) = ZPDi TP24 Y2 clock after switch
- CH3 (blue) = ZPDi TP33 Y2 Frame bits after switch
ZPDi: Frame bits timing between 3 Switch XilinX's
- CH1 (yellow) = ZPDi TP31 Y0 Frame bits after switch-1
- CH2 (green) = ZPDi TP8 Y2 Frame bits before switch-3
- CH3 (blue) = ZPDi TP33 Y2 Frame bits after switch-3
- CH4 (pink) = ZPDi TP32 Y1 Frame bits after switch-2
(Y0 yellow trace appeared to be dropped when taking the picture
copy, but when we were looking at it, it was but well timed to
the other frame bits.)
ZPDi: Compare Switch XilinX output TSF clock vs ZPD clock
- CH2 (green) = ZPDi TP24 Y2 clock after switch
- CH3 (blue) = ZPDi backplane pin 2A (spare2=clk60 from ZPD)
(added on May/1/03. Note that this is just for Y2 clock after switch,
while there is a wide variation of clock times between the channels
after switch as shown earlier - the 2 X channels are 2-4ns earlier.)
ZPDi: TSF input clock damping effect for resistors
- CH2 (green) = ZPDi Y2 clock from channel link before 100Ohm resistor
- CH3 (blue) = ZPDi TP4 Y2 clock after 100Ohm resistor
(added May/1/03)
ZPDi: TSF input clock effect of removing damping resistors
- CH2 (green) = ZPDi TP9 X4 clock with 100Ohm resistor shorted over
- CH3 (blue) = ZPDi TP4 Y2 clock after 100Ohm resistor
- CH4 (red) = ZPDi Y2 clock from channel link before 100Ohm resistor
(added May/2/03)
