DCT Upgrade Fast Control Simulation

The tests are performed with unit time simulation under Innoveda. The test package consists of FC + OP (ZPD) connecting to a test memory of 32 bit wide x 16 addresses. The simulation were done mostly with XILINX libraries for memories, although a few were done earlier with ORCA libraries.

Definitions of some of the variables in the simulation:

CMD_IN	Fast control command value at CLINK
TAG_IN	Fast control sub-command (tag)
CDATA	16 bit CLINK data latched every clock-4
CLINK	CLINK bit stream
CLINK	DLINK bit stream
FC_AD_BUS	Internal bus between FC and OP sections
MINI_BUS	16 bit address/data bus between FC/OP and memories in algorithm FPGAs
ADD_STROBE	Address strobe to memories - latch address value on MINI_BUS to memory
DATA_LOWER	Data strobe - latch lower 16 bits on MINI_BUS to memory
DATA_UPPER	Data strobe - latch upper 16 bits on MINI_BUS to memory
DATA_WIDTH	Transfer type at MINI_BUS: low=16 bit; high=32 bit
READ_WRITE	Transfer direction at MINI_BUS: low=WRITE; high=READ
MEM_ADDRESS	Current selected address at the test memory
MEM_WRITE_BUF	32 bit write buffer input to the test memory
MEM_READ_BUF	32 bit buffer at output read port of the test memory
MEM_WR_ENABLE	Strobe high to latch WRITE_BUF data to memory

CSR write/read test:

Single word memory write/read:

• Example of 32 bit write of value 'DEADBEEF' (hex) to address 5:
  


• Example of 16 bit write of value 'CAFE' (hex) to address 9:

Note the default behavior of the 16 bit memory zeroing its own upper 16 bits during the 16 bit write.


• Example of 32 bit read of a memory address (5) with value 'DEADBEEF' (hex):
  


• Example of 16 bit read of a memory address (5) with value 'DEADBEEF' (hex):
  


• Example read memory and increment address: Addresses 9,A,... were loaded with 10011111,20022222,... This a 32 bit read-increment address after setting address to 9 just before this:
  

Block write to memories:

• Example of the 32 bit block write with variable size control. This is a block write to 4 addresses starting from address 3.

  address	Value (hex)
  3	12345678
  4	23456789
  5	3456789A
  6	456789AB

  Start of the transfer:
  
  End of the transfer:
  


• Example of the 16 bit block write with variable size control. This is a block write to 5 addresses starting from address 7.

  address	Value (hex)
  7	1001
  8	2002
  9	3003
  A	4004
  B	5005

  Start of the transfer:
  
  End of the transfer:
  

Block read from memories:

• Setup of 32bit block read with command 11 to start with address 9 and read for 3 addresses:
  


• Actual 32bit block read transfer with command 12:
  Start of the block-read transfer:
  
  End of the transfer:
  



16 bit block transfer with command 12 from the same address range 
    (with a similar command 11 aubcom=0 setup preceeding this):

DAQ test:

•  Example of the a DAQ read out sequence test. Modelled the 4 DAQ buffers,
   each buffer is a combination of two physical memory buffers from separate
   block addresses. The DAQ readout will take 4 16-bit words from Mem-1 
   followed by 3 16-bit words from Mem-2 address ranges correspond to this 
   DAQ buffer. The memory address ranges and loaded data pattern are as follows:
  

  		Mem-1 (Blk=20)	Mem-2 (Blk=40)
  buffer	address	Value (hex)	Value (hex)
  0	0	11111001	1111A011
  	1	11111002	1111A012
  	2	11111003	1111A013
  	3	11111004
  1	4	22222001	2222A021
  	5	22222002	2222A022
  	6	22222003	2222A023
  	7	22222004
  2	8	33333001	3333A031
  	9	33333002	3333A032
  	A	33333003	3333A033
  	B	33333004
  3	C	44444001	4444A041
  	D	44444002	4444A042
  	E	44444003	4444A043
  	F	44444004

  and the DAQ readout is assuming 16 bit memories so that only the lower 16 bits are readout.
  Read event after L1A for buffer=1 (part 1):
  
  Read event after L1A for buffer=1 (part 2):
  
  

      Note: At the end of reading of Mem-1 data, the DAQ control has
      to spend one clock-4 to setup block address and start address
      for Mem-2. This creats a gap of exactly 1 16-bit word between
      the two pieces of data. The data value for the 'gap word' is a 
      repeat of the last word from mem-1 (2004\H).

  
  Another L1A and event readout for buffer=2:
  
  

      Note: besides the buffer contents are changing reflecting the fact
      we moved on to another buffer for the 2nd L1A, if you are following
      every DLINK bit for the header, it can be verified that the DAQ 
      buffer number is incrementing, and the local trigger counter is 
      varying (the L1A command tag is fixed to 0xB; DAQ format=2 and 
      ZPD board ID=6). The header and data are coming out with LSB 
      first overall. The bit definitions of the header are: 

  
  

  bit	value	description
  0	1	start
  1	1	reserved (flag DAQ header)
  2:6		L1A command data (trigger tag) (0:4)
  7	0	reserved
  8:12		Local trigger counter (0:4)
  13:14		DAQ buffer number (1:0)
  15	0	reserved
  16		boardID(1)
  17		boardID(0)
  18		mem_active(1) (output mem)
  19		mem_active(0) (input mem)
  20		GLINK synched
  21		GLINK locked
  22		mem_pr_mode
  23		mem_play_rec(1) (output mem)
  24		mem_enable(1) (output mem)
  25		mem_play_rec(0) (input mem)
  26		mem_enable(0) (input mem)
  27		DAQ format(1)
  28		DAQ format(0)
  29		board_id(2)
  30		Run mode(1)
  31		Run mode(0)

  Note that unfortuantely the DAQ buffer number and the top 16 bit of CSR1 read back are in the reverse bit order locally from what their normal definitions. However, as long as we know the definition, there is not much point to change the order now.