L1 DCT Upgrade Interface Documentation

Documentation on the Existing DCT Interface

DCT FDR Interface Specification (LBL directory).

Standard Trigger Fast Control Interface (LBL directory).

DIRC DCC schematics (A3 ps): [Top],[Signal protocol], [Clock distribution], [C-link], [D-link]
DIRC electronics schematics: DCC / PDB (J3 backplane)
DIRC electronics web page at LPNHE-X (directory).

DCH Trigger I/O (TIOM) document

Picture of the original TSFi.

Block diagram of the TSFi extracted from the TSF Schematic Description.

DCT backplane pins: Generic,TSF/TSFi, PTD/PTDi, DIRC J3

Upgrade Interface Engineering Design

Jeff Olsen's interface board design page

Hardware component datasheets:

• Agilent HDMP-1024 G-link receiver
• National LVDS channel link: 217/218 (21 bits), 287/288 (28-bits)
• Precision Inter Connect / SamTec cable and connector assembly

Updated Fast Control Command Document (Jul/02)

Fast control / OP control VHDL simulation (Jul/02)

Upgrade DCT backplane pins: ZPD/ZPDi, TSF/TSFi (prelim)

Pictures of ZPDi: [1],[2]

Upgrade Interface Tests / Schedule

• Current schedule,Schedule for June/03 test

• TSF->ZPD interface scope timing test (Apr/30/03)

• TSFi->TSF GLINK test (May/6/03)

• ZPD->GLT interface scope test (May 19-20, 2003)

• TSF neighbor scope test (Jul 24, 2003)

• Zpdi patched wire test (Aug 13, 2003)

• DCT/DCZ latency test (Feb 24, 2004)

Upgrade Interface Test Status

• TSF to ZPD Cabling

Upgrade Interface Specifications

CDR Interface document

Interface Block Diagrams: TSFi/TSF,ZDPi/ZPD, GLTi/GLT

DCH to TSF GLINK wire map
TSF neighbor data wire map
TSF<->TSFi signal electrical spec
TSF slow monitoring issues

TSF->ZPD data packet design
ZPDi TSF->ZPD segment switch map
ZPD->GLT signal map

A diagram of ZPD input data phi span.
Plots of ZPD phi span vs Pt: Forward track, Backward track
Philip Hart's early interface studies

Some useful general information

National LVDS page, General Introduction to LVDS.

DCH layer geometry table.