GLT Cabling Information            Update:  Jan/23/03
 ======================= 

 There are two aspects of the GLT cabling which require attention for
 people touching this part of the hardware or trying to study hardware
 signals in/out of the GLTi interface: 
 
 1) There are 10 EMT cables coming to GLTi, each carrying 1/10th of 
    phi worth of information (2 bits each for M,G,E,X and 1 bit of Y).
    The GLTi sockets are labelled for TPB 1-10, corresponding to the   
    sections of the EMT starting of increasing phi from phi=0. 
    However, the original EMT cables also labelled TPB 1-10 were 
    actually EMT1-9,EMT0. Simply matchinging TPB 1-10 labels between
    EMT calble and GLTi socket would cause a one cable (1/10 of 360) 
    rotation. The correct cabling should be:       
       Old EMT cable label       GLT socket      
           TPB-10                  TPB-1
           TPB-1                   TPB-2
           TPB-2                   TPB-3
            ...                      .. 
           TPB-9                   TPB-10
    A new set of labels are now wrapped on top of the old EMT cable 
    labels (Jan/03) to clarify the connection map. 

 2) The GLT ad GLTi was originally built with the assumption that
    8 PTDs are covering 2 1/16 phi sectors each with PTD-0 covering
    the 2 phi sectors from phi=0-45 degrees in the standard convention. 
    However, the actual PTD-0 was covering the two sections from
    -22.5 to 22.5 degrees (for a good reason: only needs data from 
    2 TSFYs instead of 3 compared to the phi=0-45 span case). This one 
    bit shift unfortunately has no simple solution of rotating cables
    as it staggers PTD boundaries. So we had to make a kluge fix on
    the GLT board itself in the FPGA signal pin routing: 
      Connector AP0  ->  GLT internal signal  AP15
                AP1  ->                       AP0   
                 ..                           ..
                AP15 ->                       AP14
    So GLT internally and software wise we only see the standard 
    definition AP with LSB starting from phi=0 so that users dealing
    with data through software will not notice this shift. However, 
    if you are probing on GLTi, or looking at signals on the backplane
    pins following the signal names there, then the AP pins are 
    in the uncorrected PTD form. In the era of ZPDs, the ZPDs actually
    follow the standard convention of starting at phi=0 boundary 
    so that the ZPD signal coming through the same GLT backplane
    pins as the current AP will be deliberately rotated off inside 
    the GLTi switch FPGA (so that they are offset in the same way as
    PTD at the GLT backplane) and then corrected back at the GLT 
    receiver FPGA pin input.