The following information is obtained from Maurizio Lo Vetere and experimentation since run 5:

The IFS has two series of jumpers near the FPGA. The names are LATENCY SELECTION (L0-4) and OUTPUT WITDH SELECTION JMP (3 CK8 TICKS/ 1 CK8 TICKS).
Please don't pay attention to the names. The names have been superceeded when we reprogrammed the FPGA to deal with LST in March 2005. 
Each row has three pins and the jumpers may be placed in two position (left or right).

Jumpers under the name LATENCY SELECTION should not be changed as in the picture below were the lines (----) represent the jumpers.
              
The configuration for run 5 was:
                                                                       
                  LATENCY      0    x    1  SELECTION
                  L0           (----)
                  L1           (----)
                  L2                  (----)
                  L3           (----)

                  OUTPUT   WIDTH            SELECTION
                  JMP          (----)
                               3         1
                               C         C
                               K         K
                               8         8
                                      
The configuration for run 6 and onward is:
                           
                  LATENCY      0    x    1  SELECTION
                  L0           (----)
                  L1           (----)
                  L2           (----)
                  L3                  (----)

                  OUTPUT   WIDTH            SELECTION
                  JMP               (----)
                               3         1
                               C         C
                               K         K
                               8         8
   
Note that for run6 onward, the jumper under OUTPUT WIDTH SELECTION has been changed to reflect the fact that all the barrel is instrumented with LST otherwise the IFS code will assume RPC signals in layers 0.2.3.5 and would treat them in a wrong way.

More information about the latency:
  
L3-L2 is a global delay of the signals going to glt and it acts irrespectively of the input.
L1-L0 is an extra delay for RPC wrt LST. 
Both delays have a resolution of an clk8. The value is coded on 2 bits each. With the present configuration L1-L0 affects only the endcaps and L3-L2 both endcaps and barrel.
L3-L2 should be adjusted looking at the timing of the barrel wrt. other detectors. After this L1-L0 should be adjusted looking at the timing of the endcaps wrt. to all the other detectors.