Fast Control Protocol for EMC Trigger             11/11/98
=====================================             ========

Op-code      1E
Command      User reset
Subcommand   0
Data         None
Description  Reset control register to a specified state and zero error
             register. Reset Xilinx's (_reset line). Equivalent to power cycle.

Op-code      1D
Command      Clear playback FIFO's
Subcommand   0
Data         None
Description  Resets the read pointers of the playback FIFO's, ready for new
             series of read commands.

Op-code      1C
Command      Reset playback FIFO's
Subcommand   0
Data         None
Description  Resets the write pointers of the playback FIFO's, ready for new
             series of write commands.

Op-code      1B
Command      Write memory
Subcommand   0-6, 8-10 and 13
Data         Byte stream, length implicitly defined as below.
Description  Writes memory to address specified by the subcommand. Valid
             addresses and number of bytes are;
              A0-3 for the algorithm Xilinx configuration data    88 bytes
              A4-6 for the front end playback FIFO's            2048 bytes
              A8   for the back end playback FIFO               2048 bytes
              A9   for the formatter Xilinx bitmask               32 bytes
              A10  for the latency buffer offsets                  8 bytes
              A13  for the control register (plus dummy byte)      2 bytes
             Note, the front and back end playback FIFO's are each 16kbytes
             but the ROM buffer size is 4kbytes including the header. Hence,
             the data will be sent in 2kbyte packets and so require 8 writes
             to completely fill the memories. In the initial test-stand using
             the RAL2301, the buffer size is only 512bytes and hence filling
             the memories will require 32 writes.
             The algorithm Xilinx and latency data require the readback header
             to be prepended to the data, which adds 2 bytes to the above
             numbers.

Op-code      1A
Command      Read Memory
Subcommand   0-6, 8-10 and 12
Data         None
Description  Reads memory at address specified by the subcommand. Valid
             addresses and number of bytes are;
              A0-3 for the algorithm Xilinx configuration data    88 bytes
              A4-6 for the front end playback FIFO's            2048 bytes
              A8   for the back end playback FIFO               2048 bytes
              A9   for the formatter Xilinx bitmask               32 bytes
              A10  for the latency buffer offsets                  8 bytes
              A12  for the control, status and error registers
                   and the serial number and geometric address     6 bytes
             Note, the front and back end playback FIFO's require multiple
             reads as detailed above.

Op-code      19
Command      Set to run mode
Subcommand   0
Data         None
Description  Sets first control register bit to run mode. None of the
             other control bits are changed.

Op-code      18
Command      Set to configure mode
Subcommand   0
Data         None
Description  Sets first control register bit to configure mode. None of the
             other control bits are changed.

Op-code      16
Command      Clear Spy FIFO
Subcommand   0
Data         None
Description  Resets spy FIFO pointers.

Op-code      15
Command      Clear Errors
Subcommand   0
Data         None
Description  Zeros error flags