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Calorimeter L1 Trigger Hardware Document Repository
Contains the latest documents for the EMT
- Overall System Level
- Crate
- Trigger Carrier Board
- Trigger Processor Board
- External Interface Specifications Documents
- Interface to EMC ROM/UPC,
Connector Pin Layout,
EMT/EMC Map,
EMC/EMT Map with Cable Info (last update 13/11/2002 TL),
UPC Numerology,
UPC Writeup,
Cable labels (original),
UPC Cable labels (replacement panel Aug/03)
- UPC Clock Phase Problem (Sept/03)
- Interface to GLT
- Interface to Fast Control: Protocol
- Interface to DAQ: Full Trigger Description
- Latency Estimate
- Replacement Patch Panel:
Patch Panel Connections,
Conceptual Panel Layout,
Schematics,
Layout Top (inside view),
Layout Bottom (outside view),
Old Panel Map,
New Panel Map (TPBs 0-4),
New Panel Map (TPBs 5-9)
- Internal Interface Specifications Documents
- Algorithm Xilinx (AX)
- Fast Control Xilinx (FCX)
- Formatter Xilinx (FX)
- VME Xilinx (VX)
- Hardware and Spares
- TPB's: 2 pre-production (S/N 16-17), 13 production (S/N 18-30)
- TCB's: 4 production (S/N 1-4)
- Crates: 2 chassis, 3 21-slot standard J1 backplanes, 4 12-slot custom J2/3 backplanes,
3 5-slot standard J2 backplanes, 4 5-slot custom J3 backplanes
- Various: VME custom board extender, TPB components spares box, PROM's
- Current location
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