Old TSF memory map (Su Dong Jul/03 reading from VHDL) ================== Block 0x1 Input memory-1 32k x 20 0x2 Input memory-2 32k x 20 Input memory 1,2 playback are interleaved such that actual data flowing into the board is taking each memory in turn. (added by jamie oct 8 04) - the tsf input memories both should have 7 padding 0's before the data so the input data is correctly used. 0x3 PTD output mem 32k x 32 0x4 BLT output mem 32k x 8 For each TSF's 4-bit data package over the 4 clock30 ticks: TSFX bits TSFY bits clk30 tick 0 1 2 3 0 1 2 3 0 1a 1b 2a 2b 5a 5b 5c 5d 1 3a 3b 4a 4b - - - - 2 8a 8b 9a 9b 6a 6b 6c 6d 3 10a 10b - - 7a 7b 7c 7d where e.g. 8b means Superlayer 8 supercell b and supercell a-b (for TSFX) or a-d (for TSFY) are the supercells within each TSF in increasing phi order. Note: the actual signals carried onto backplane is: pin BLT1 = bit 3 pin BLT2 = bit 2 pin BLT3 = bit 1 pin BLT4 = bit 0 0x5 Mask memory 21 16-bit words serial R/W olnly 0x6 Version mem a single register of 16 bits 0x7 DAQ offset a 5-bit word 0x8 Engine 0 LUT 64k x 16 A0: X:A10a Y:A7b 0x9 Engine 1 LUT 64k x 16 A1: X:A10b Y:A7d 0xa Engine 2 LUT 64k x 16 A2: X:A4a Y:A7a 0xb Engine 3 LUT 64k x 16 A3: X:A4b Y:A7c 0xc Engine 4 LUT 64k x 16 A4: X:A1 Y: - 0xd Engine 5 LUT 64k x 16 S0: X:U2a Y:U5a 0xe Engine 6 LUT 64k x 16 S1: X:U2b Y:U5c 0xf Engine 7 LUT 64k x 16 S2: X:V3a Y:U5b 0x10 Engine 8 LUT 64k x 16 S3: X:V3b Y:U5d 0x11 Engine 9 LUT 64k x 16 S4: X:V9a Y:V6a 0x12 Engine 10 LUT 64k x 16 S5: X:V9b Y:V6b 0x13 Engine 11 LUT 64k x 16 S6: X:U8a Y:V6c 0x14 Engine 12 LUT 64k x 16 S7: X:U8b Y:V6d