GLT Configuration Information

Viewing GLT Configuration Information

The GLT configurations parameters store in the online Database are eventually mapped to the various registers and memories on the GLT board, some are directly loaded to registers while others such as the 8Mb LUT and the trigger line cuts are derived from the DB parameters. These parameters are controlled from two separate sources:

• TrigConfig controls the trigger line parameters: object count cuts to define trigger lines; trigger line latching widths; trigger line `SVT trick' fine delays. The viewing of these parameters are best done through the getTrgConfig utility following the instructions at this link. A general introduction of the GLT trigger objects can be found on this page,  while a detailed history of the major trigger configuration changes are documented at the trigger configuration history page.

• The GltConfig TC controls the other parameters: input/output/DAQ delays, object counting rules, DCT/EMT match options etc. The GLT config TC content can be examined through the CfgExplorer which can be run from any release (on preferrably) Ambientboot. You can navigate through the numeric list (a tree with some key symbols), GLT->L1GltConfig:Default which should give a list of existing L1GltConfig keys (13 up to Mar/06). Double click on any key will bring the object details. To find out which GLT key is used by which run, you need to navigate from the numeric list from Top->CfgTopMap then find in the long list of keys the top key for that run. The object detail should have an item ~Glt/L1GltConfig indicating the L1GltConfig key. Another useful command line tool to find out which top Alias is using which L1GltConfig key:  BdbCfgTool  AliasSnapshot glt.     

The actual snapshot of the L1GltCOnfig objects can be viewed for Key 1 and Key 9 representing the bulk of data taken for old DCT system 2001-2004 and with new DCZ since 2005 respectively. Some explanations of the various sections of the L1GltConfig object: 

• LUT skip parameters:  these are the minimum phi bin separation for counting phi objects as distinct. e.g. skip=1 means only objects with |phi1-phi2|>=2 are counted as separate objects while two adjacent phi bins hit only counts as 1 object. The GLT configuration code in the ROM will take these parameters to generate the actual 8Mb LUT on the fly at configuration time.  
• InputDelayDR*: These are the input primitive timing alignment delays for FPGAs DR1 and DR2. The delays are in clock8 ticks defined as follows:  

  Bits	DR1 reg 0x500	DCT before 2005	DCZ since 2005
  0:3	U	3	2
  4:7	G	0	0
  8:11	E	0	0
  12:15	Y	0	0
  16:19	M	0	0
  	DR2 reg 0x500
  0:3	B	8	4
  4:7	Ap	0	0
  8:11	A	8	4
  12:15	X	0	0

  InputDelayDR1: 3     means only IFR U is delayed by 3 ticks, while all EMT delays=0.  
  InputDelayDR2: 808 means only BLT A,B delayed by 8 while Ap,X delays=0. 

  Note: 

  • IFT U delay change 3->2 was not related to DCZ, but happened to also started in 2005 when LST moved to IFR top/bottom. We used to have 1/2 tick difference between U with others so that we took the chance changed IFT U stretch from 3 to 4 ticks to line up better with others.
  • Ap and X in the DCZ era are both from ZPD. 
  • TSF latency for BLT data changed for the new TSFs in DCZ which resulted in a increased latency for the BLT path.   
     
• Matchoption:  corresponds to the the M&C FPGA register 0 value. For the old DCT era the values were the DCT+EMT phi match options (=how many EMT M bins closest to the DCT A,B,Ap bin are classified as a match, for AM,BM,Apm; how many closest DCT B bins for an EMT M/X bin).  In the DCZ era the match objects were replaced by ZPD Z objects so that the matching parameters became mostly irrelevant, except the EZ* parameter is the closest

  Bits	0:3	4:7	8:11	12:15
  Old DCT	AM	BM	APM	BMX
  New DCZ	-	-	-	EZ*

  The old matching phi options had been set to=3 for all match objects throughout the running before DCT replacement in 2005. This rather tight choice was used an an effective intermediate Pt cut for BM in particular. The register parameter setting has a problem since repalcement for DCZ, but EZ* has so far not yet been used for any configuration.

• MCversion:  M&C FPAG frimware version 0=old DCT; 1=DCZ
• SelectDelay: Select FPGA register 0x3. (0:7)= fine delay; (8:12)=coarse delay
  This is used to make a global output delay to all trigger lines. The fine delay is in 1ns(?) unit to 
  allow optimal output signal phasing w.r.t. FCT. 
• IDAQ Delay: IDAQ register 0x500 bits 0:5  Latency offset parameter (in clock8)
• ODAQ Delay: ODAQ register 0x500 bits (0:5)=Obj count delay; (8:13)=Rawlines delay  Latency offset parameter (in clock8).
• ODAQ trg Delay: ODAQ register 0x501 bits 0:5 Latency for snatching the trigger output into ODAQ (This is very sensitive and should not be changed).

GLT Object configuration

ZPD Input primitive mapping to old GLT 

First implementation of ZPD objects common cuts: -2<tandip<3;  Z0err<15;  (A7|A10) for all.