----------------------------------------------------------------------------
-- Lawrence Berkeley National Laboratory (c) 1997
-- BaBar Trigger Electronics
----------------------------------------------------------------------------
-- Description:  
--    Serial to parallel shift register
----------------------------------------------------------------------------
-- Author:   Armin Karcher
-- History:
--    Karcher    03/97 - First Version
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

----------------------------------------------------------------------------
--PORT DECLARATION
----------------------------------------------------------------------------

entity ser2par is
  port	(clk 	: in  std_logic;	-- clk60 input, distributed
	rst 	: in  std_logic;	-- global reset
	clink 	: in  std_logic;	-- serial data in
	data	: out  std_logic_vector(15 downto 0); -- data out
	shift3	: out std_logic);	-- contents of register bit 3
					-- same as data(3)
end ser2par;

architecture rtl of ser2par is

----------------------------------------------------------------------------
--SIGNAL DECLARATION
----------------------------------------------------------------------------
  signal reg_val: std_logic_vector(15 downto 0); -- contents of register

begin
 
----------------------------------------------------------------------------
--PROCESS DECLARATION
----------------------------------------------------------------------------
 shift_reg: process (clk,rst,clink)
  begin
    if (rst = '1') then
      reg_val <= "0000000000000000";
    elsif (clk'event and clk = '1') then
      reg_val(15) <= reg_val(14);
      reg_val(14) <= reg_val(13);
      reg_val(13) <= reg_val(12);
      reg_val(12) <= reg_val(11);
      reg_val(11) <= reg_val(10);
      reg_val(10) <= reg_val(9);
      reg_val(9) <= reg_val(8);
      reg_val(8) <= reg_val(7);
      reg_val(7) <= reg_val(6);
      reg_val(6) <= reg_val(5);
      reg_val(5) <= reg_val(4);
      reg_val(4) <= reg_val(3);
      reg_val(3) <= reg_val(2);
      reg_val(2) <= reg_val(1);
      reg_val(1) <= reg_val(0);
      reg_val(0) <= clink;
    end if;
  end process;

----------------------------------------------------------------------------
--OUTPUT ASSIGNMENTS
----------------------------------------------------------------------------
   data <= reg_val;
   shift3 <= reg_val(3);

end rtl;