----------------------------------------------------------------------------
-- Lawrence Berkeley National Laboratory (c) 1997
-- BaBar Trigger Electronics
----------------------------------------------------------------------------
-- Description:  
--    Not a true fifo, this 32 bit wide by 4 bit deep dual port RAM stores 
--    trigger information. A read and write pointer control access.
----------------------------------------------------------------------------
-- Structure:
-- l1_fifo
-- sdpram	-- SCUBA generated dual port RAM, slightly modified (see code)
-- cntrs	-- read and write pointer counters.
-- i_latch	-- latch data to make writing easier
----------------------------------------------------------------------------
-- Author:   Armin Karcher
-- History:
--    Karcher    03/97 - First Version
--	Karcher	6/4/97 - Duplicated addresses for DOUT fanout
--   Grace      5/11/98- Fixed trigger tag
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

----------------------------------------------------------------------------
--PORT DECLARATION
----------------------------------------------------------------------------

entity l1_fifo is

  port	(clk 	: in  std_logic;	-- clk60 input, distributed
	rst 	: in  std_logic;	-- global reset
	adv_cmd_str	: in  std_logic;	-- strobe on cycle 13 after 
				    -- the begin of a 12 bit command sequence
	cmd_str	: in  std_logic;	-- strobe on cycle 14
	l1 	: in  std_logic;	-- level1 accept
	rd_evt 	: in  std_logic;	-- read event
	clr_rd 	: in  std_logic;	-- clear readout
	tag	: in  std_logic_vector(4 downto 0); -- latched trigger tag
	ctr	: in  std_logic_vector(4 downto 0); -- trigger time
	csr_val	: in  std_logic_vector(15 downto 0); -- csr contents at trigger
	wr_buf1	: out  std_logic_vector(1 downto 0); -- write pointer
	rd_buf1	: out  std_logic_vector(1 downto 0); -- read pointer
	wr_buf2	: out  std_logic_vector(1 downto 0); -- write pointer duplicate
	rd_buf2	: out  std_logic_vector(1 downto 0); -- read pointer duplicate
	data_out: out  std_logic_vector(31 downto 0) -- data out
        );
end l1_fifo;

architecture rtl of l1_fifo is

----------------------------------------------------------------------------
--SIGNAL DECLARATION
----------------------------------------------------------------------------
  signal i_reg_val: std_logic_vector(31 downto 0); -- latched data
  signal raddr1: std_logic_vector(1 downto 0);	   -- read pointer
  signal waddr1: std_logic_vector(1 downto 0);	   -- write pointer
  signal raddr2: std_logic_vector(1 downto 0);	   -- read pointer duplicate
  signal waddr2: std_logic_vector(1 downto 0);	   -- write pointer duplicate
  signal wr_1: std_logic;			   -- write strobe 
  signal lag_cmd_str: std_logic;		   -- strobe on cycle 15
----------------------------------------------------------------------------
--COMPONENT DECLARATION
----------------------------------------------------------------------------

  component sdpram
    port (waddr: in std_logic_vector(1 downto 0);
	  datain: in std_logic_vector(31 downto 0); 
          clk: in std_logic;
	  wren: in std_logic; 
	  raddr: in std_logic_vector(1 downto 0); 
          dataout: out std_logic_vector(31 downto 0));
  end component;

begin

memory: sdpram
port map (waddr1,i_reg_val,clk,wr_1,raddr1,data_out);
 
----------------------------------------------------------------------------
--PROCESS DECLARATION
----------------------------------------------------------------------------
 i_latch: process (clk,rst,l1,cmd_str)
  begin
    if (rst = '1') then
      i_reg_val <= "00000000000000000000000000000000";
      wr_1 <= '0';
      lag_cmd_str <= '0';
    elsif (clk'event and clk = '1' ) then
      wr_1 <= (l1 AND lag_cmd_str);
      if (l1 = '1' AND lag_cmd_str = '1') then
        i_reg_val(31) <= '1';  
        i_reg_val(30) <= '1';  
        i_reg_val(29 downto 25) <= tag;  
        i_reg_val(24) <= '0';  
        i_reg_val(23) <= ctr(0);  
        i_reg_val(22) <= ctr(1);  
        i_reg_val(21) <= ctr(2);  
        i_reg_val(20) <= ctr(3);  
        i_reg_val(19) <= ctr(4);  
        i_reg_val(18 downto 17) <= waddr1;  
        i_reg_val(16) <= '0';  
        i_reg_val(15 downto 0) <= csr_val;  
      end if;
    lag_cmd_str <= cmd_str;
    end if;

  end process;

 cnters: process (clk,rst,l1,adv_cmd_str)
  begin
    if (rst = '1') then
      raddr1 <= "00";
      waddr1 <= "00";
      raddr2 <= "00";
      waddr2 <= "00";
    elsif (clk'event and clk = '1' ) then
      if ( clr_rd = '1' AND adv_cmd_str = '1') then
        raddr1 <= "00";
        waddr1 <= "00";
        raddr2 <= "00";
        waddr2 <= "00";
      else
	if (l1 = '1' AND adv_cmd_str = '1') then
          waddr1(0) <= NOT waddr1(0);  
          waddr1(1) <= waddr1(0) XOR waddr1(1);  
          waddr2(0) <= NOT waddr2(0);  
          waddr2(1) <= waddr2(0) XOR waddr2(1);  
        end if;
        if (rd_evt = '1' AND adv_cmd_str = '1') then
          raddr1(0) <= NOT raddr1(0);  
          raddr1(1) <= raddr1(0) XOR raddr1(1);  
          raddr2(0) <= NOT raddr2(0);  
          raddr2(1) <= raddr2(0) XOR raddr2(1);  
        end if;
      end if;
    end if;
  end process;

----------------------------------------------------------------------------
--OUTPUT ASSIGNMENTS
----------------------------------------------------------------------------
wr_buf1 <= waddr1;
rd_buf1 <= raddr1;
wr_buf2 <= waddr2;
rd_buf2 <= raddr2;

end rtl;