----------------------------------------------------------------------------
-- Lawrence Berkeley National Laboratory (c) 1997
-- BaBar Trigger Electronics
----------------------------------------------------------------------------
-- Description:  
-- This entity generates the lower speed clocks (clk30 ... clk2) and the 
-- 5 bit trigger time tag using an up counter. This counter is reset to zero 
-- on a sync command.
----------------------------------------------------------------------------
-- Structure:
-- cntr: 5 bit counter with asynchronous and synchronous reset
----------------------------------------------------------------------------
-- Timing:
--    The clk30 rising edge comes on the first clk60 tick after a sync
----------------------------------------------------------------------------
-- Author:   Armin Karcher
-- History:
--    Karcher    03/97 - First Version
--	Karcher	6/3/97 - moved clock fanout to produce multipe FFs
--	Karcher	8/25/97 - removed clock fanout
----------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
----------------------------------------------------------------------------
--PORT DECLARATION
----------------------------------------------------------------------------
 
entity clk_divide is
  port(
	clk 	 : in std_logic;	-- clk60 input, distributed
	rst 	 : in std_logic;	-- global reset
	sync 	 : in std_logic;	-- sync command, resets counter
	adv_cmd_str : in std_logic;	-- this strobe qualifies sync one 
					-- tick before the actual cmd_str
	clk_30   : out std_logic_vector(4 downto 0);	-- lower speed clocks
	clk_15   : out std_logic;	-- lower speed clocks
	clk_8   : out std_logic;	-- lower speed clocks
	clk_4   : out std_logic;	-- lower speed clocks
	clk_2   : out std_logic;	-- lower speed clocks
	ctr      : out std_logic_vector(4 downto 0)  -- trigger time tag
  );
end clk_divide;

architecture rtl of clk_divide is
----------------------------------------------------------------------------
--SIGNAL DECLARATION
----------------------------------------------------------------------------
  signal clks0   :  std_logic_vector(4 downto 0); -- internal count result
  signal clks1   :  std_logic;
  signal clks2   :  std_logic;
  signal clks3   :  std_logic;
  signal clks4   :  std_logic;
  signal ctr_i : signed (4 downto 0);		-- 5 bit counter input
  signal ctr_o : signed (4 downto 0);		-- 5 bit counter output
  signal clks0_i : signed (4 downto 0);		-- counter input
  signal clks0_o : signed (4 downto 0);		-- counter output
begin

----------------------------------------------------------------------------
--PROCESS DECLARATION
----------------------------------------------------------------------------

  ctr_i <= ctr_o;
  clks0_i <= clks0_o;

  cntr: process (clk,rst)		-- 4/5 bit counter
  begin
   if (rst = '1') then			-- reset all variables
      ctr_o <= "00000";
      clks0_o <= "00000";
      clks1 <= '0';
      clks2 <= '0';
      clks3 <= '0';
      clks4 <= '0';
   elsif (clk'event and clk = '1') then 	-- rising edge
     if (adv_cmd_str = '1' AND sync ='1') then
      ctr_o <= "00000";			-- synchronous reset
      clks0_o <= "00000";
      clks1 <= '0';
      clks2 <= '0';
      clks3 <= '0';
      clks4 <= '0';
     else
      ctr_o <= ctr_i + 1;
      clks0_o <= clks0_i + 1;
      clks1 <= NOT clks1;
      clks2 <= NOT clks2;
      clks3 <= NOT clks3;
      clks4 <= NOT clks4;
     end if;
   end if;
  end process cntr;

  clks0 <= std_logic_vector(clks0_o);
 
----------------------------------------------------------------------------
--OUTPUT ASSIGNMENTS
----------------------------------------------------------------------------
 clk_30(0) <= clks0(0);
 clk_30(1) <= clks1;
 clk_30(2) <= clks2;
 clk_30(3) <= clks3;
 clk_30(4) <= clks4;
  clk_15 <= clks0(1);
  clk_8 <= clks0(2);
  clk_4 <= clks0(3);
  clk_2 <= clks0(4);
 ctr <= std_logic_vector(ctr_o);
end rtl;